[flang-commits] [clang] [flang] [lldb] [llvm] [mlir] [NFC] Silence -Wbool-integral-comparison warnings across LLVM (PR #195246)
Andrei Sabalenka via flang-commits
flang-commits at lists.llvm.org
Sat May 2 14:51:09 PDT 2026
https://github.com/mechakotik updated https://github.com/llvm/llvm-project/pull/195246
>From ad6d7cf0867728be8e4c4a71a5e8bc3eff103bdc Mon Sep 17 00:00:00 2001
From: Andrei Sabalenka <mechakotik at gmail.com>
Date: Fri, 1 May 2026 12:21:37 +0300
Subject: [PATCH] [NFC] Silence -Wbool-integral-comparison warnings across LLVM
---
bolt/lib/Profile/BoltAddressTranslation.cpp | 4 ++--
clang/lib/CodeGen/CodeGenFunction.cpp | 2 +-
clang/lib/Serialization/ASTReaderStmt.cpp | 4 ++--
flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp | 2 +-
flang/unittests/Evaluate/uint128.cpp | 14 +++++++-------
lldb/source/ValueObject/ValueObject.cpp | 3 ++-
llvm/include/llvm/CodeGen/DIE.h | 4 ++--
llvm/include/llvm/Support/DataExtractor.h | 2 +-
llvm/lib/ExecutionEngine/JITLink/aarch32.cpp | 2 +-
llvm/lib/Support/DataExtractor.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp | 3 ++-
.../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +-
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++-
llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 2 +-
mlir/lib/Rewrite/ByteCode.cpp | 2 +-
16 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/bolt/lib/Profile/BoltAddressTranslation.cpp b/bolt/lib/Profile/BoltAddressTranslation.cpp
index 2068c9efbcb44..cc404e1aef70f 100644
--- a/bolt/lib/Profile/BoltAddressTranslation.cpp
+++ b/bolt/lib/Profile/BoltAddressTranslation.cpp
@@ -185,7 +185,7 @@ template <bool Cold>
void BoltAddressTranslation::writeMaps(uint64_t &PrevAddress, raw_ostream &OS) {
const uint32_t NumFuncs =
llvm::count_if(llvm::make_first_range(Maps), [&](const uint64_t Address) {
- return Cold == ColdPartSource.count(Address);
+ return Cold == (ColdPartSource.count(Address) != 0);
});
encodeULEB128(NumFuncs, OS);
LLVM_DEBUG(dbgs() << "Writing " << NumFuncs << (Cold ? " cold" : "")
@@ -194,7 +194,7 @@ void BoltAddressTranslation::writeMaps(uint64_t &PrevAddress, raw_ostream &OS) {
for (auto &MapEntry : Maps) {
const uint64_t Address = MapEntry.first;
// Only process cold fragments in cold mode, and vice versa.
- if (Cold != ColdPartSource.count(Address))
+ if (Cold != (ColdPartSource.count(Address) != 0))
continue;
// NB: in `writeMaps` we use the input address because hashes are saved
// early in `saveMetadata` before output addresses are assigned.
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index b920266b59808..ad208c924a183 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -175,7 +175,7 @@ void CodeGenFunction::CGFPOptionsRAII::ConstructorHelper(FPOptions FPFeatures) {
auto mergeFnAttrValue = [&](StringRef Name, bool Value) {
auto OldValue =
CGF.CurFn->getFnAttribute(Name).getValueAsBool();
- auto NewValue = OldValue & Value;
+ bool NewValue = OldValue && Value;
if (OldValue != NewValue)
CGF.CurFn->addFnAttr(Name, llvm::toStringRef(NewValue));
};
diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp
index 4ada1dc58042d..288eb345e4818 100644
--- a/clang/lib/Serialization/ASTReaderStmt.cpp
+++ b/clang/lib/Serialization/ASTReaderStmt.cpp
@@ -155,7 +155,7 @@ void ASTStmtReader::VisitCompoundStmt(CompoundStmt *S) {
SmallVector<Stmt *, 16> Stmts;
unsigned NumStmts = Record.readInt();
unsigned HasFPFeatures = Record.readInt();
- assert(S->hasStoredFPFeatures() == HasFPFeatures);
+ assert(static_cast<unsigned>(S->hasStoredFPFeatures()) == HasFPFeatures);
while (NumStmts--)
Stmts.push_back(Record.readSubStmt());
S->setStmts(Stmts);
@@ -1160,7 +1160,7 @@ void ASTStmtReader::VisitCastExpr(CastExpr *E) {
CurrentUnpackingBits.emplace(Record.readInt());
E->setCastKind((CastKind)CurrentUnpackingBits->getNextBits(/*Width=*/7));
unsigned HasFPFeatures = CurrentUnpackingBits->getNextBit();
- assert(E->hasStoredFPFeatures() == HasFPFeatures);
+ assert(static_cast<unsigned>(E->hasStoredFPFeatures()) == HasFPFeatures);
E->setSubExpr(Record.readSubExpr());
diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
index 5a4e517c13ef5..76280c1636897 100644
--- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
+++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp
@@ -966,7 +966,7 @@ bool PPCIntrinsicLibrary::isNativeVecElemOrderOnLE() {
bool PPCIntrinsicLibrary::changeVecElemOrder() {
const auto triple{fir::getTargetTriple(builder.getModule())};
return (triple.isLittleEndian() !=
- converter->getLoweringOptions().getNoPPCNativeVecElemOrder());
+ (converter->getLoweringOptions().getNoPPCNativeVecElemOrder() != 0));
}
static mlir::FunctionType genMmaVpFuncType(mlir::MLIRContext *context,
diff --git a/flang/unittests/Evaluate/uint128.cpp b/flang/unittests/Evaluate/uint128.cpp
index 0b749abe1c080..3d0e1b7e6e84c 100644
--- a/flang/unittests/Evaluate/uint128.cpp
+++ b/flang/unittests/Evaluate/uint128.cpp
@@ -66,13 +66,13 @@ static void TestVsNative(__uint128_t x, __uint128_t y) {
TEST(ToNative(n) == y);
TEST(ToNative(~m) == ~x);
TEST(ToNative(-m) == -x);
- TEST(ToNative(!m) == !x);
- TEST(ToNative(m < n) == (x < y));
- TEST(ToNative(m <= n) == (x <= y));
- TEST(ToNative(m == n) == (x == y));
- TEST(ToNative(m != n) == (x != y));
- TEST(ToNative(m >= n) == (x >= y));
- TEST(ToNative(m > n) == (x > y));
+ TEST(ToNative(!m) == static_cast<__uint128_t>(!x));
+ TEST(ToNative(m < n) == static_cast<__uint128_t>(x < y));
+ TEST(ToNative(m <= n) == static_cast<__uint128_t>(x <= y));
+ TEST(ToNative(m == n) == static_cast<__uint128_t>(x == y));
+ TEST(ToNative(m != n) == static_cast<__uint128_t>(x != y));
+ TEST(ToNative(m >= n) == static_cast<__uint128_t>(x >= y));
+ TEST(ToNative(m > n) == static_cast<__uint128_t>(x > y));
TEST(ToNative(m & n) == (x & y));
TEST(ToNative(m | n) == (x | y));
TEST(ToNative(m ^ n) == (x ^ y));
diff --git a/lldb/source/ValueObject/ValueObject.cpp b/lldb/source/ValueObject/ValueObject.cpp
index 33f143bb4e3e2..99f5aad03d16e 100644
--- a/lldb/source/ValueObject/ValueObject.cpp
+++ b/lldb/source/ValueObject/ValueObject.cpp
@@ -357,8 +357,9 @@ bool ValueObject::IsLogicalTrue(Status &error) {
LazyBool is_logical_true = language->IsLogicalTrue(*this, error);
switch (is_logical_true) {
case eLazyBoolYes:
+ return true;
case eLazyBoolNo:
- return (is_logical_true == true);
+ return false;
case eLazyBoolCalculate:
break;
}
diff --git a/llvm/include/llvm/CodeGen/DIE.h b/llvm/include/llvm/CodeGen/DIE.h
index 92265fd86ebb9..6ab1f9c9994f9 100644
--- a/llvm/include/llvm/CodeGen/DIE.h
+++ b/llvm/include/llvm/CodeGen/DIE.h
@@ -547,7 +547,7 @@ struct IntrusiveBackListBase {
void push_back(Node &N) {
assert(N.Next.getPointer() == &N && "Expected unlinked node");
- assert(N.Next.getInt() == true && "Expected unlinked node");
+ assert(N.Next.getInt() && "Expected unlinked node");
if (Last) {
N.Next = Last->Next;
@@ -558,7 +558,7 @@ struct IntrusiveBackListBase {
void push_front(Node &N) {
assert(N.Next.getPointer() == &N && "Expected unlinked node");
- assert(N.Next.getInt() == true && "Expected unlinked node");
+ assert(N.Next.getInt() && "Expected unlinked node");
if (Last) {
N.Next.setPointerAndInt(Last->Next.getPointer(), false);
diff --git a/llvm/include/llvm/Support/DataExtractor.h b/llvm/include/llvm/Support/DataExtractor.h
index ec935e7e10564..dace45e9a8fa0 100644
--- a/llvm/include/llvm/Support/DataExtractor.h
+++ b/llvm/include/llvm/Support/DataExtractor.h
@@ -99,7 +99,7 @@ class DataExtractor {
/// Get the data pointed to by this extractor.
StringRef getData() const { return Data; }
/// Get the endianness for this extractor.
- bool isLittleEndian() const { return IsLittleEndian; }
+ bool isLittleEndian() const { return IsLittleEndian != 0; }
/// Extract a C string from \a *offset_ptr.
///
diff --git a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
index 2f3234683bf55..2df5bcb42b9e0 100644
--- a/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
@@ -915,7 +915,7 @@ bool StubsManager_v7::visitEdge(LinkGraph &G, Block *B, Edge &E) {
});
}
- assert(MakeThumb == (StubSymbol->getTargetFlags() & ThumbSymbol) &&
+ assert(MakeThumb == hasTargetFlags(*StubSymbol, ThumbSymbol) &&
"Instruction set states of stub and relocation site should be equal");
LLVM_DEBUG({
dbgs() << " Using " << (MakeThumb ? "Thumb" : "Arm") << " entry "
diff --git a/llvm/lib/Support/DataExtractor.cpp b/llvm/lib/Support/DataExtractor.cpp
index 6b58b492002fd..8385888c3cb9c 100644
--- a/llvm/lib/Support/DataExtractor.cpp
+++ b/llvm/lib/Support/DataExtractor.cpp
@@ -48,7 +48,7 @@ T DataExtractor::getU(uint64_t *offset_ptr, Error *Err) const {
if (!prepareRead(offset, sizeof(T), Err))
return val;
std::memcpy(&val, &Data.data()[offset], sizeof(val));
- if (sys::IsLittleEndianHost != IsLittleEndian)
+ if (sys::IsLittleEndianHost != isLittleEndian())
sys::swapByteOrder(val);
// Advance the offset
@@ -150,7 +150,7 @@ uint64_t DataExtractor::getUnsigned(uint64_t *offset_ptr, uint32_t byte_size,
(sys::IsLittleEndianHost ? 0 : 8 - byte_size),
&Data.data()[offset], byte_size);
// Swap the least significant bytes of val if endianness doesn't match.
- if (sys::IsLittleEndianHost != IsLittleEndian)
+ if (sys::IsLittleEndianHost != isLittleEndian())
val = sys::getSwappedBytes(val) >> (8 * (8 - byte_size));
*offset_ptr += byte_size;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
index f6fe48bf5bb49..d43363f1a0f85 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
@@ -567,7 +567,8 @@ class llvm::AMDGPUNextUseAnalysisImpl {
const auto &ToInit = R ? ReachablePaths : UnreachablePaths;
for (const Path &P : ToInit) {
PathInfo &Slot = getOrInitPathInfo(P.src(), P.dst());
- assert(Slot.isForwardReachableUnset() || Slot.ForwardReachable == R);
+ assert(Slot.isForwardReachableUnset() ||
+ Slot.ForwardReachable == static_cast<int>(R));
Slot.ForwardReachable = R;
}
}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 7b5738845ef2c..1bb45253090fc 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6223,7 +6223,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
return Error(IDRange.Start, "directive requires gfx8+", IDRange);
if (!isUInt<1>(Val))
return OutOfRangeError(ValRange);
- if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())
+ if ((Val != 0) != getTargetStreamer().getTargetID()->isXnackOnOrAny())
return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",
IDRange);
} else if (ID == ".amdhsa_float_round_mode_32") {
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 8c54d292dbd1c..c6976447b508d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1316,7 +1316,7 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
bool IsPacked, bool HasDstSel) {
- int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
+ bool DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
for (int I = 0; I < NumOps; ++I) {
if (!!(Ops[I] & Mod) != DefaultValue)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d3df8a3203d81..989db49085e8c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5219,7 +5219,8 @@ static bool isAlternating(const std::array<std::pair<int, int>, 2> &SrcInfo,
bool C = Src == SrcInfo[1].first && Diff == SrcInfo[1].second;
assert(C != (Src == SrcInfo[0].first && Diff == SrcInfo[0].second) &&
"Must match exactly one of the two slides");
- if (RequiredPolarity != (C == (Idx / Factor) % 2))
+ bool OddGroup = ((Idx / Factor) % 2) != 0;
+ if (RequiredPolarity != (C == OddGroup))
return false;
}
return true;
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index c02ff857cd3eb..42c370c49997a 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -13281,7 +13281,7 @@ struct AANoAliasAddrSpaceImpl : public AANoAliasAddrSpace {
ChangeStatus updateImpl(Attributor &A) override {
unsigned FlatAS = A.getInfoCache().getFlatAddressSpace().value();
- uint32_t OldAssumed = getAssumed();
+ bool OldAssumed = getAssumed();
auto CheckAddressSpace = [&](Value &Obj) {
if (isa<PoisonValue>(&Obj))
diff --git a/mlir/lib/Rewrite/ByteCode.cpp b/mlir/lib/Rewrite/ByteCode.cpp
index 2daf2635d96d5..85c8451f37e10 100644
--- a/mlir/lib/Rewrite/ByteCode.cpp
+++ b/mlir/lib/Rewrite/ByteCode.cpp
@@ -1441,7 +1441,7 @@ void ByteCodeExecutor::executeApplyConstraint(PatternRewriter &rewriter) {
processNativeFunResults(results, numResults, rewriteResult);
// Depending on the constraint jump to the proper destination.
- selectJump(isNegated != succeeded(rewriteResult));
+ selectJump((isNegated != 0) != succeeded(rewriteResult));
}
LogicalResult ByteCodeExecutor::executeApplyRewrite(PatternRewriter &rewriter) {
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