[flang-commits] [clang] [flang] [llvm] [mlir] [polly] Enforce single-operand form for llvm.loop.vectorize metadata (PR #210932)
via flang-commits
flang-commits at lists.llvm.org
Tue Jul 21 03:19:52 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Madhur Amilkanthwar (madhur13490)
<details>
<summary>Changes</summary>
This patch implements Phase 2 of the RFC "Enforce Single-Operand Format for All .enable Metadata Nodes". The two-operand boolean form !{!"llvm.loop.vectorize.enable", i1 0/1} is replaced by a single-operand enable/disable pair:
!{!"llvm.loop.vectorize.enable"} ; force vectorization
!{!"llvm.loop.vectorize.disable"} ; suppress vectorization
The Verifier rejects the two-operand form, AutoUpgrade rewrites old bitcode (including the legacy llvm.vectorizer.enable tag), and the readers and producers across LLVM, Clang, MLIR and Polly are updated.
Please refer to RFC:
https://discourse.llvm.org/t/rfc-enforce-single-operand-format-for-all-enable-metadata-nodes/90571/
---
Patch is 161.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210932.diff
213 Files Affected:
- (modified) clang/lib/CodeGen/CGLoopInfo.cpp (+6-8)
- (modified) clang/test/CodeGenCXX/pragma-followup_inner.cpp (+1-1)
- (modified) clang/test/CodeGenCXX/pragma-followup_outer.cpp (+1-1)
- (modified) clang/test/CodeGenCXX/pragma-loop-pr27643.cpp (+1-1)
- (modified) clang/test/CodeGenCXX/pragma-loop-predicate.cpp (+1-1)
- (modified) clang/test/CodeGenCXX/pragma-loop-safety.cpp (+1-1)
- (modified) clang/test/CodeGenCXX/pragma-loop.cpp (+1-1)
- (modified) clang/test/OpenMP/for_simd_codegen.cpp (+4-4)
- (modified) clang/test/OpenMP/for_simd_scan_codegen.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_safelen.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_simd.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_simd_aligned.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_simdlen.cpp (+1-1)
- (modified) clang/test/OpenMP/irbuilder_simdlen_safelen.cpp (+1-1)
- (modified) clang/test/OpenMP/master_taskloop_simd_codegen.cpp (+4-4)
- (modified) clang/test/OpenMP/parallel_for_simd_codegen.cpp (+5-5)
- (modified) clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp (+1-1)
- (modified) clang/test/OpenMP/simd_codegen.cpp (+1-1)
- (modified) clang/test/OpenMP/simd_metadata.c (+1-1)
- (modified) clang/test/OpenMP/target_simd_codegen.cpp (+4-4)
- (modified) clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp (+2-2)
- (modified) clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp (+2-2)
- (modified) clang/test/OpenMP/taskloop_simd_codegen.cpp (+1-1)
- (modified) clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp (+2-2)
- (modified) clang/test/OpenMP/teams_distribute_simd_codegen.cpp (+1-1)
- (modified) clang/test/PCH/delayed-template-with-pragma.cpp (+1-1)
- (modified) clang/tools/clang-fuzzer/proto-to-llvm/loop_proto_to_llvm.cpp (+5-5)
- (modified) flang/test/Integration/ivdep.f90 (+1-1)
- (modified) flang/test/Integration/vector-always.f90 (+2-2)
- (modified) llvm/docs/LangRef.md (+4-6)
- (modified) llvm/docs/TransformMetadata.rst (+3-3)
- (modified) llvm/include/llvm/IR/AutoUpgrade.h (+6-1)
- (modified) llvm/lib/Bitcode/Reader/MetadataLoader.cpp (+3)
- (modified) llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp (+2-4)
- (modified) llvm/lib/IR/AutoUpgrade.cpp (+59-3)
- (modified) llvm/lib/IR/Verifier.cpp (+8)
- (modified) llvm/lib/Transforms/Utils/LoopConstrainer.cpp (+1-2)
- (modified) llvm/lib/Transforms/Utils/LoopUtils.cpp (+3-3)
- (modified) llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp (+8)
- (modified) llvm/test/Bitcode/upgrade-loop-metadata.ll (+1-1)
- (added) llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll (+37)
- (added) llvm/test/Bitcode/upgrade-loop-vectorize-enable.ll.bc ()
- (modified) llvm/test/Transforms/IRCE/add-metadata-pre-post-loops.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/correct-loop-info.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/loop-guarded-bounds.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/pre_post_loops.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/range_intersect_miscompile.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/unsigned_comparisons_ugt.ll (+1-1)
- (modified) llvm/test/Transforms/IRCE/unsigned_comparisons_ult.ll (+1-1)
- (modified) llvm/test/Transforms/Inline/dilocation-loop-metadata-update.ll (+2-2)
- (modified) llvm/test/Transforms/InstCombine/mem-par-metadata-memcpy.ll (+1-1)
- (modified) llvm/test/Transforms/LoopIdiom/AArch64/disable-vectorize.ll (+2-2)
- (modified) llvm/test/Transforms/LoopRotate/vect.omp.persistence.ll (+2-2)
- (modified) llvm/test/Transforms/LoopTransformWarning/enable_and_isvectorized.ll (+1-1)
- (modified) llvm/test/Transforms/LoopTransformWarning/optnone.ll (+1-1)
- (modified) llvm/test/Transforms/LoopTransformWarning/vectorization-remarks-missed.ll (+1-1)
- (modified) llvm/test/Transforms/LoopTransformWarning/vectorizer-loop-kind-unroll-warning.ll (+1-1)
- (modified) llvm/test/Transforms/LoopUnroll/unroll-pragmas-disabled.ll (+2-2)
- (modified) llvm/test/Transforms/LoopUnroll/vectorizer-loop-kind-remarks.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/call-costs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/masked_ldst_sme.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/optsize_minsize.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-mixed.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-predicate-instruction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions-tf.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-basic-vec.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-extract-last-veclane.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-inv-store.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-large-strides.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-masked-loadstore.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-type-conv.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-extractvalue.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/unsafe-vf-hint-remark.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/vplan-native-outer-loop-wide-type.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/widen-gep-all-indices-invariant.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/optsize_minsize.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-fixed-order-recurrence.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-vp-intrinsics-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/constant-fold.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-outer-loop.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls-finite.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/cost-model.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-VF2-VF8.ll (+17-17)
- (modified) llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls-finite.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/libm-vector-calls.ll (+13-13)
- (modified) llvm/test/Transforms/LoopVectorize/X86/no_fpmath.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/outer-loop-non-power-of-2-type.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/redundant-vf2-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs-max-bandwidth.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/svml-calls-finite.ll (+14-14)
- (modified) llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/alias-mask.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/diag-disabled-vectorization-msgs.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/disable_nonforced_enable.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no-fold-tail-by-masking-iv-external-uses.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no_array_bounds.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no_switch.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/no_switch_disable_vectorization.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/optsize.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer-loop-atomic.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer-loop-vec-phi-predecessor-order.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_early_exit.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/reduction-inloop.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/remove_metadata.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/runtime-check-threshold-with-force-metadata.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/runtime-check.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/scalable-inductions.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/unsafe-vf-hint-remark.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-predicated-early-exit.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-outer-loop-uncomputable-trip-count.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll (+1-1)
- (modified) llvm/test/Transforms/PhaseOrdering/AArch64/Oz-and-forced-vectorize.ll (+1-1)
- (modified) llvm/test/Transforms/PhaseOrdering/X86/loop-vectorize-metadata.ll (+2-2)
- (modified) llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll (+1-1)
- (modified) llvm/test/Transforms/SROA/mem-par-metadata-sroa.ll (+1-1)
- (modified) llvm/test/Transforms/SimplifyCFG/X86/combine-parallel-mem-md.ll (+1-1)
- (modified) llvm/test/Verifier/llvm.loop-cu-strip-followup.ll (+2-2)
- (added) llvm/test/Verifier/llvm.loop.vectorize.ll (+41)
- (modified) mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp (+3-2)
- (modified) mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp (+6-1)
- (modified) mlir/test/Target/LLVMIR/Import/import-failure.ll (-16)
- (modified) mlir/test/Target/LLVMIR/Import/metadata-loop.ll (+1-1)
- (modified) mlir/test/Target/LLVMIR/loop-metadata.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-parallel-do-simd.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-simd-ordered.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-simd-reduction-byref.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-teams-distribute-parallel-do-simd.mlir (+1-1)
- (modified) mlir/test/Target/LLVMIR/openmp-wsloop-simd-ordered.mlir (+1-1)
- (modified) polly/lib/CodeGen/CodeGeneration.cpp (+17-1)
- (modified) polly/lib/CodeGen/IRBuilder.cpp (+4-5)
- (modified) polly/test/CodeGen/MemAccess/create_arrays.ll (+1-1)
- (modified) polly/test/CodeGen/Metadata/basic_vec_annotate.ll (+2-2)
- (modified) polly/test/CodeGen/Metadata/fallback_vec_annotate.ll (+1-1)
- (modified) polly/test/CodeGen/annotated_alias_scopes.ll (+1-1)
- (modified) polly/test/CodeGen/scev-backedgetaken.ll (+1-1)
- (modified) polly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll (+1-1)
``````````diff
diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp
index 6b0b1b55213e1..b46ae34e58a44 100644
--- a/clang/lib/CodeGen/CGLoopInfo.cpp
+++ b/clang/lib/CodeGen/CGLoopInfo.cpp
@@ -209,10 +209,8 @@ clang::CodeGen::LoopInfo::createLoopVectorizeMetadata(
SmallVector<Metadata *, 4> NewLoopProperties;
if (Enabled == false) {
NewLoopProperties.append(LoopProperties.begin(), LoopProperties.end());
- NewLoopProperties.push_back(
- MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"),
- ConstantAsMetadata::get(ConstantInt::get(
- llvm::Type::getInt1Ty(Ctx), 0))}));
+ NewLoopProperties.push_back(MDNode::get(
+ Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.disable")}));
LoopProperties = NewLoopProperties;
}
return createUnrollAndJamMetadata(Attrs, LoopProperties, HasUserTransforms);
@@ -279,10 +277,10 @@ clang::CodeGen::LoopInfo::createLoopVectorizeMetadata(
(Attrs.VectorizeScalable == LoopAttributes::Disable &&
Attrs.VectorizeWidth != 1)) {
VectorizeEnabled = Attrs.VectorizeEnable != LoopAttributes::Disable;
- Args.push_back(
- MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"),
- ConstantAsMetadata::get(ConstantInt::get(
- llvm::Type::getInt1Ty(Ctx), VectorizeEnabled))}));
+ Args.push_back(MDNode::get(
+ Ctx, {MDString::get(Ctx, VectorizeEnabled
+ ? "llvm.loop.vectorize.enable"
+ : "llvm.loop.vectorize.disable")}));
}
// Apply all loop properties to the vectorized loop.
diff --git a/clang/test/CodeGenCXX/pragma-followup_inner.cpp b/clang/test/CodeGenCXX/pragma-followup_inner.cpp
index 04f5656dcd638..20615d9744c6e 100644
--- a/clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ b/clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -25,7 +25,7 @@ extern "C" void followup_inner(int n, int *x) {
// CHECK-DAG: ![[DISTRIBUTE_5]] = !{!"llvm.loop.distribute.enable", i1 true}
// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6]] = !{!"llvm.loop.distribute.followup_all", ![[PARALLEL_ACCESSES_4]], ![[VECTORIZE_8:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[OUTERLOOP_9]] = distinct !{![[OUTERLOOP_9]], [[MP:![0-9]+]], ![[UNROLLANDJAM_COUNT_10:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10]] = !{!"llvm.loop.unroll_and_jam.count", i32 4}
diff --git a/clang/test/CodeGenCXX/pragma-followup_outer.cpp b/clang/test/CodeGenCXX/pragma-followup_outer.cpp
index fdd5a07d00857..70ce57c6fb6a7 100644
--- a/clang/test/CodeGenCXX/pragma-followup_outer.cpp
+++ b/clang/test/CodeGenCXX/pragma-followup_outer.cpp
@@ -22,7 +22,7 @@ extern "C" void followup_outer(int n, int *x) {
// CHECK-DAG: ![[DISTRIBUTE_5:[0-9]+]] = !{!"llvm.loop.distribute.enable", i1 true}
// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]] = !{!"llvm.loop.distribute.followup_all", [[MP]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[VECTORIZE_8:[0-9]+]], ![[VECTORIZE_FOLLOWUP_9:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[VECTORIZE_FOLLOWUP_9:[0-9]+]] = !{!"llvm.loop.vectorize.followup_all", [[MP]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_11:[0-9]+]], ![[UNROLLANDJAM_12:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPOUTER_13:[0-9]+]]}
// CHECK-DAG: ![[ISVECTORIZED_11:[0-9]+]] = !{!"llvm.loop.isvectorized"}
diff --git a/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp b/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
index 37e29776264b6..afab64f4c6867 100644
--- a/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-pr27643.cpp
@@ -43,7 +43,7 @@ void loop4(int *List, int Length) {
// CHECK: ![[LOOP1]] = distinct !{![[LOOP1]], [[MP:![0-9]+]], ![[VEC_WIDTH_1:.*]], ![[FIXED_WIDTH:.*]], ![[VEC_ENABLE:.*]]}
// CHECK: ![[VEC_WIDTH_1]] = !{!"llvm.loop.vectorize.width", i32 1}
// CHECK: ![[FIXED_WIDTH]] = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
-// CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: ![[LOOP2]] = distinct !{![[LOOP2]], [[MP]], ![[VEC_WIDTH_2:.*]], ![[FIXED_WIDTH:.*]], ![[VEC_ENABLE]]}
// CHECK: ![[VEC_WIDTH_2]] = !{!"llvm.loop.vectorize.width", i32 2}
diff --git a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
index 8a25ed8de6239..421110fd9f867 100644
--- a/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-predicate.cpp
@@ -103,7 +103,7 @@ void test9(int *List, int Length) {
// CHECK: ![[LOOP0]] = distinct !{![[LOOP0]], [[MP:![0-9]+]], [[GEN3:![0-9]+]]}
// CHECK: [[MP]] = !{!"llvm.loop.mustprogress"}
-// CHECK-NEXT: [[GEN3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-NEXT: [[GEN3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-NEXT: ![[LOOP1]] = distinct !{![[LOOP1]], [[MP]], [[GEN6:![0-9]+]], [[GEN3]]}
// CHECK-NEXT: [[GEN6]] = !{!"llvm.loop.vectorize.predicate.enable", i1 true}
diff --git a/clang/test/CodeGenCXX/pragma-loop-safety.cpp b/clang/test/CodeGenCXX/pragma-loop-safety.cpp
index db1b6769e0514..e2a7a124890a6 100644
--- a/clang/test/CodeGenCXX/pragma-loop-safety.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop-safety.cpp
@@ -51,7 +51,7 @@ void interleave_test(int *List, int Length) {
// CHECK: ![[PARALLEL_ACCESSES_7]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_2]]}
// CHECK: ![[UNROLL_DISABLE]] = !{!"llvm.loop.unroll.disable"}
// CHECK: ![[INTERLEAVE_1]] = !{!"llvm.loop.interleave.count", i32 1}
-// CHECK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: ![[ACCESS_GROUP_8]] = distinct !{}
// CHECK: ![[LOOP2_HINTS]] = distinct !{![[LOOP2_HINTS]], [[MP]], ![[PARALLEL_ACCESSES_11:[0-9]+]], ![[UNROLL_DISABLE]], ![[WIDTH_1:[0-9]+]], ![[INTENABLE_1]]}
// CHECK: ![[PARALLEL_ACCESSES_11]] = !{!"llvm.loop.parallel_accesses", ![[ACCESS_GROUP_8]]}
diff --git a/clang/test/CodeGenCXX/pragma-loop.cpp b/clang/test/CodeGenCXX/pragma-loop.cpp
index 8cb3346247daf..d4a9faaf2be6b 100644
--- a/clang/test/CodeGenCXX/pragma-loop.cpp
+++ b/clang/test/CodeGenCXX/pragma-loop.cpp
@@ -256,7 +256,7 @@ void for_test_interleave_vectorize_disable_unroll(int *List, int Length) {
// CHECK-DAG: ![[INTERLEAVE_10:[0-9]+]] = !{!"llvm.loop.interleave.count", i32 10}
// CHECK-DAG: ![[INTERLEAVE_16:[0-9]+]] = !{!"llvm.loop.interleave.count", i32 16}
-// CHECK-DAG: ![[VECTORIZE_ENABLE:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: ![[VECTORIZE_ENABLE:[0-9]+]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-DAG: ![[FIXED_VEC:[0-9]+]] = !{!"llvm.loop.vectorize.scalable.enable", i1 false}
// CHECK-DAG: ![[SCALABLE_VEC:[0-9]+]] = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
// CHECK-DAG: ![[WIDTH_1:[0-9]+]] = !{!"llvm.loop.vectorize.width", i32 1}
diff --git a/clang/test/OpenMP/for_simd_codegen.cpp b/clang/test/OpenMP/for_simd_codegen.cpp
index 1ac95e8943640..ae6161d03978d 100644
--- a/clang/test/OpenMP/for_simd_codegen.cpp
+++ b/clang/test/OpenMP/for_simd_codegen.cpp
@@ -802,10 +802,10 @@ void parallel_simd(float *a) {
}
// TERM_DEBUG: !{{[0-9]+}} = !DILocation(line: [[@LINE-11]],
// TERM_DEBUG-NOT: line: 0,
-// OMP45-NOT: !"llvm.loop.vectorize.enable", i1 false
+// OMP45-NOT: !"llvm.loop.vectorize.disable"
// CHECK-DAG: ![[SIMD_LOOP]] = distinct !{![[SIMD_LOOP]], {{.*}}![[VECT_LOOP:[^,]+]]}
-// CHECK-DAG: ![[VECT_LOOP]] = !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP45-NOT: !"llvm.loop.vectorize.enable", i1 false
+// CHECK-DAG: ![[VECT_LOOP]] = !{!"llvm.loop.vectorize.enable"}
+// OMP45-NOT: !"llvm.loop.vectorize.disable"
// OMP50-DAG: ![[NOSIMD_LOOP]] = distinct !{![[NOSIMD_LOOP]], {{.*}}![[NOVECT_LOOP:[^,]+]]}
-// OMP50-DAG: ![[NOVECT_LOOP]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP50-DAG: ![[NOVECT_LOOP]] = !{!"llvm.loop.vectorize.disable"}
#endif // HEADER
diff --git a/clang/test/OpenMP/for_simd_scan_codegen.cpp b/clang/test/OpenMP/for_simd_scan_codegen.cpp
index 829f2656042fb..9ab62f8a682b2 100644
--- a/clang/test/OpenMP/for_simd_scan_codegen.cpp
+++ b/clang/test/OpenMP/for_simd_scan_codegen.cpp
@@ -300,5 +300,5 @@ void baz(int n) {
}
#endif
-// CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: !{!"llvm.loop.vectorize.enable"}
diff --git a/clang/test/OpenMP/irbuilder_safelen.cpp b/clang/test/OpenMP/irbuilder_safelen.cpp
index 6a4266f9646a7..3090eafa6a508 100644
--- a/clang/test/OpenMP/irbuilder_safelen.cpp
+++ b/clang/test/OpenMP/irbuilder_safelen.cpp
@@ -250,7 +250,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 45}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
// CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
-// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META4]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP5]] = distinct !{}
// CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META3]]}
diff --git a/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp b/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
index 210978fc6069c..215b37e4bbb5f 100644
--- a/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
+++ b/clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
@@ -252,7 +252,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP2]] = distinct !{}
// CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]], [[META5:![0-9]+]], [[META6:![0-9]+]]}
// CHECK: [[META4]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP2]]}
-// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META6]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP7]] = distinct !{}
// CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META9:![0-9]+]], [[META5]]}
diff --git a/clang/test/OpenMP/irbuilder_simd.cpp b/clang/test/OpenMP/irbuilder_simd.cpp
index 9c36e4ab97182..03f92d8117d45 100644
--- a/clang/test/OpenMP/irbuilder_simd.cpp
+++ b/clang/test/OpenMP/irbuilder_simd.cpp
@@ -65,7 +65,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: ![[META3:[0-9]+]] = distinct !{}
// CHECK-NEXT: ![[META4]] = distinct !{![[META4]], ![[META5:[0-9]+]], ![[META6:[0-9]+]]}
// CHECK-NEXT: ![[META5]] = !{!"llvm.loop.parallel_accesses", ![[META3]]}
-// CHECK-NEXT: ![[META6]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-NEXT: ![[META6]] = !{!"llvm.loop.vectorize.enable"}
// CHECK-NEXT: ![[META7:[0-9]+]] = distinct !{}
// CHECK-NEXT: ![[META8]] = distinct !{![[META8]], ![[META9:[0-9]+]], ![[META6]]}
// CHECK-NEXT: ![[META9]] = !{!"llvm.loop.parallel_accesses", ![[META7]]}
diff --git a/clang/test/OpenMP/irbuilder_simd_aligned.cpp b/clang/test/OpenMP/irbuilder_simd_aligned.cpp
index b5ce43c8ea6a9..bb121036b4f0c 100644
--- a/clang/test/OpenMP/irbuilder_simd_aligned.cpp
+++ b/clang/test/OpenMP/irbuilder_simd_aligned.cpp
@@ -293,7 +293,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP4]] = distinct !{}
// CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
// CHECK: [[META6]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP4]]}
-// CHECK: [[META7]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META7]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[ACC_GRP8]] = distinct !{}
// CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META10:![0-9]+]], [[META7]]}
// CHECK: [[META10]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP8]]}
diff --git a/clang/test/OpenMP/irbuilder_simdlen.cpp b/clang/test/OpenMP/irbuilder_simdlen.cpp
index f6c26923851d0..9a7e8d5332ae0 100644
--- a/clang/test/OpenMP/irbuilder_simdlen.cpp
+++ b/clang/test/OpenMP/irbuilder_simdlen.cpp
@@ -252,7 +252,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[ACC_GRP2]] = distinct !{}
// CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]], [[META5:![0-9]+]], [[META6:![0-9]+]]}
// CHECK: [[META4]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP2]]}
-// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META5]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META6]] = !{!"llvm.loop.vectorize.width", i32 3}
// CHECK: [[ACC_GRP7]] = distinct !{}
// CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META9:![0-9]+]], [[META5]]}
diff --git a/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp b/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
index e46d5dde841b3..bb35f9341ded4 100644
--- a/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
+++ b/clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
@@ -250,7 +250,7 @@ void simple(float *a, float *b, int *c) {
// CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 45}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
// CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
-// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[META3]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[META4]] = !{!"llvm.loop.vectorize.width", i32 2}
// CHECK: [[ACC_GRP5]] = distinct !{}
// CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META7:![0-9]+]], [[META3]]}
diff --git a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
index d78d193e2edd1..f1eae642b613c 100644
--- a/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
+++ b/clang/test/OpenMP/master_taskloop_simd_codegen.cpp
@@ -238,10 +238,10 @@ struct S {
// CHECK: br label %{{.*}}!llvm.loop
// CHECK: ret i32 0
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP50-DAG: !{!"llvm.loop.vectorize.enable", i1 false}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// OMP50-DAG: !{!"llvm.loop.vectorize.disable"}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 4}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 32}
// CHECK-DAG: !{!"llvm.loop.vectorize.width", i32 8}
diff --git a/clang/test/OpenMP/parallel_for_simd_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_codegen.cpp
index 40af7069bbf7d..cc8cab706975a 100644
--- a/clang/test/OpenMP/parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_simd_codegen.cpp
@@ -798,16 +798,16 @@ for (int i = 0; i < 10; ++i);
// OMP50: omp.inner.for.body:
// OMP50: %{{[0-9]+}} = atomicrmw add ptr %{{[0-9]+}}, i32 1 monotonic, align 4, !llvm.access.group !{{[0-9]+}}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// OMP45-DAG: ![[VECT]] = distinct !{![[VECT]], ![[PA:.+]], ![[VM:.+]]}
// OMP45-DAG: ![[PA]] = !{!"llvm.loop.parallel_accesses", !{{.+}}}
-// OMP45-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable", i1 true}
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable"}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
// OMP50-DAG: ![[VECT]] = distinct !{![[VECT]], ![[PA:.+]], ![[VM:.+]]}
// OMP50-DAG ![[PA]] = !{!"llvm.loop.parallel_accesses", !{{.+}}}
-// OMP50-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// OMP50-DAG: ![[VM]] = !{!"llvm.loop.vectorize.enable"}
// OMP50-DAG: ![[NOVECT]] = distinct !{![[NOVECT]], ![[NOVM:.+]]}
-// OMP50-DAG: ![[NOVM]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP50-DAG: ![[NOVM]] = !{!"llvm.loop.vectorize.disable"}
// TERM_DEBUG-LABEL: bar
int bar() { extern void mayThrow(); mayThrow(); return 0; };
diff --git a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
index cac997753d480..e3810c27163a4 100644
--- a/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
+++ b/clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp
@@ -299,7 +299,7 @@ void baz(int n) {
}
}
-// CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: !{!"llvm.loop.vectorize.enable"}
#endif
diff --git a/clang/test/OpenMP/simd_codegen.cpp b/clang/test/OpenMP/simd_codegen.cpp
index b96e4213e8e0e..ee8d709ba47fe 100644
--- a/clang/test/OpenMP/simd_codegen.cpp
+++ b/clang/test/OpenMP/simd_codegen.cpp
@@ -861,7 +861,7 @@ S8 s8(0);
// TERM_DEBUG-NOT: line: 0,
// TERM_DEBUG: distinct !DISubprogram(linkageName: "_GLOBAL__sub_I_simd_codegen.cpp",
-// OMP5-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP5-DAG: ![[NOVECT:.+]] = !{!"llvm.loop.vectorize.disable"}
// OMP5-DAG: ![[DISABLE_VECT]] = distinct !{{.*}}![[NOVECT]]{{[,}]}}
#endif // HEADER
diff --git a/clang/test/OpenMP/simd_metadata.c b/clang/test/OpenMP/simd_metadata.c
index 83bcbf6deefe2..6fc4c401135f2 100644
--- a/clang/test/OpenMP/simd_metadata.c
+++ b/clang/test/OpenMP/simd_metadata.c
@@ -109,7 +109,7 @@ void h3(float *c, float *a, float *b, int size)
// Metadata for h1:
// CHECK: [[LOOP_H1_HEADER:![0-9]+]] = distinct !{[[LOOP_H1_HEADER]], [[LOOP_WIDTH_16:![0-9]+]], [[LOOP_VEC_ENABLE:![0-9]+]]}
// CHECK: [[LOOP_WIDTH_16]] = !{!"llvm.loop.vectorize.width", i32 16}
-// CHECK: [[LOOP_VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK: [[LOOP_VEC_ENABLE]] = !{!"llvm.loop.vectorize.enable"}
// CHECK: [[LOOP_H1_HEADER:![0-9]+]] = distinct !{[[LOOP_H1_HEADER]], [[LOOP_WIDTH_8:![0-9]+]], [[LOOP_VEC_ENABLE]]}
// CHECK: [[LOOP_WIDTH_8]] = !{!"llvm.loop.vectorize.width", i32 8}
// CHECK: ![[ACCESS_GROUP_7]] = distinct !{}
diff --git a/clang/test/OpenMP/target_simd_codegen.cpp b/clang/test/OpenMP/target_simd_codegen.cpp
index 0c2dde23f6c46..59284c201bb30 100644
--- a/clang/test/OpenMP/target_simd_codegen.cpp
+++ b/clang/test/OpenMP/target_simd_codegen.cpp
@@ -702,9 +702,9 @@ int bar(int n){
// Store captures in the context.
// CHECK-DAG: [[REF_B:%.+]] = load ptr, ptr [[LOCAL_B]],
-// OMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// TOMP45-NOT: !{!"llvm.loop.vectorize.enable", i1 false}
-// OMP51: !{!"llvm.loop.vectorize.enable", i1 false}
-// TOMP51: !{!"llvm.loop.vectorize.enable", i1 false}
+// OMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// TOMP45-NOT: !{!"llvm.loop.vectorize.disable"}
+// OMP51: !{!"llvm.loop.vectorize.disable"}
+// TOMP51: !{!"llvm.loop.vectorize.disable"}
#endif
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
index 42e8377bd22dd..fd2d0d0c18737 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration.cpp
@@ -455,7 +455,7 @@ int bar(int a){
// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2STILi100EE3fooEv", i32 {{[0-9]+}}, i32 0, i32 {{[0-9]+}}}
// TCHECK-DAG: = !{i32 0, i32 [[DEVID]], i32 [[FILEID]], !"_ZN2SCC1Ev", i32 {{[0-9]+}}, i32 0, i32 {{[0-9]+}}}
-// TCHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
+// TCHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
#endif
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
index b63f0b6caeee2..c169d4a556bf0 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_codegen_registration_naming.cpp
@@ -82,6 +82,6 @@ int nested(int a){
// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", i32 [[T1L]], i32 0, i32 {{[0-9]+}}}
// TCHECK-DAG: = !{i32 0, i32 {{-?[0-9]+}}, i32 {{-?[0-9]+}}, !"[[NNAME]]", i32 [[T2L]], i32 0, i32 {{[0-9]+}}}
-// CHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
-// TCHECK-DAG: !{!"llvm.loop.vectorize.enable", i1 true}
+// CHECK-DAG: !{!"llvm.loop.vectorize.enable"}
+// TCHECK-DAG: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210932
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