[flang-commits] [flang] 5cd8f2f - [CodeGen] Rename prologpeilog to prolog-epilog (#207870)
via flang-commits
flang-commits at lists.llvm.org
Mon Jul 6 18:26:11 PDT 2026
Author: Aiden Grossman
Date: 2026-07-06T18:26:05-07:00
New Revision: 5cd8f2f847101effad54a88936abe5e3bcb7e884
URL: https://github.com/llvm/llvm-project/commit/5cd8f2f847101effad54a88936abe5e3bcb7e884
DIFF: https://github.com/llvm/llvm-project/commit/5cd8f2f847101effad54a88936abe5e3bcb7e884.diff
LOG: [CodeGen] Rename prologpeilog to prolog-epilog (#207870)
This is primarily to ensure consistenct with the new pass manager where
the name of the pass is already prolog-epilog, which is more consistent
with our existing naming scheme. This is necessary to be able to run
existing llc invocations that explicitly specify prolog-epilog under the
NewPM automatically.
Assisted by Gemini.
Added:
Modified:
flang/test/Driver/fsave-optimization-record.f90
lld/test/ELF/lto/stats-file-option.ll
llvm/docs/Remarks.rst
llvm/include/llvm/Passes/MachinePassRegistry.def
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
llvm/test/CodeGen/AArch64/addg_subg.mir
llvm/test/CodeGen/AArch64/cfi_restore.mir
llvm/test/CodeGen/AArch64/chkstk.ll
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
llvm/test/CodeGen/AArch64/extra-callee-save.mir
llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
llvm/test/CodeGen/AArch64/framelayout-sve.mir
llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
llvm/test/CodeGen/AArch64/machine-outliner.mir
llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
llvm/test/CodeGen/AArch64/pr157252.mir
llvm/test/CodeGen/AArch64/preserve.ll
llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
llvm/test/CodeGen/AArch64/reloc-specifiers.mir
llvm/test/CodeGen/AArch64/settag-merge.mir
llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
llvm/test/CodeGen/AArch64/sve-calling-convention.ll
llvm/test/CodeGen/AArch64/sve-ld1r.mir
llvm/test/CodeGen/AArch64/sve-ldN.mir
llvm/test/CodeGen/AArch64/sve-ldnf1.mir
llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
llvm/test/CodeGen/AArch64/sve-stN.mir
llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
llvm/test/CodeGen/AArch64/wineh-frame0.mir
llvm/test/CodeGen/AArch64/wineh-frame1.mir
llvm/test/CodeGen/AArch64/wineh-frame2.mir
llvm/test/CodeGen/AArch64/wineh-frame3.mir
llvm/test/CodeGen/AArch64/wineh-frame4.mir
llvm/test/CodeGen/AArch64/wineh-frame5.mir
llvm/test/CodeGen/AArch64/wineh-frame6.mir
llvm/test/CodeGen/AArch64/wineh-frame7.mir
llvm/test/CodeGen/AArch64/wineh-frame8.mir
llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
llvm/test/CodeGen/AArch64/wineh1.mir
llvm/test/CodeGen/AArch64/wineh2.mir
llvm/test/CodeGen/AArch64/wineh3.mir
llvm/test/CodeGen/AArch64/wineh4.mir
llvm/test/CodeGen/AArch64/wineh5.mir
llvm/test/CodeGen/AArch64/wineh6.mir
llvm/test/CodeGen/AArch64/wineh7.mir
llvm/test/CodeGen/AArch64/wineh8.mir
llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
llvm/test/CodeGen/AMDGPU/frame-index.mir
llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
llvm/test/CodeGen/AMDGPU/spill-agpr.mir
llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
llvm/test/CodeGen/AMDGPU/spillv16.mir
llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
llvm/test/CodeGen/ARM/fpoffset_overflow.mir
llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
llvm/test/CodeGen/ARM/machine-outliner-calls.mir
llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
llvm/test/CodeGen/ARM/pei-swiftself.mir
llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
llvm/test/CodeGen/ARM/stack_frame_offset.mir
llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
llvm/test/CodeGen/M68k/CollapseMOVEM.mir
llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir
llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
llvm/test/CodeGen/Mips/copy-fp64.ll
llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
llvm/test/CodeGen/PowerPC/aix-csr.ll
llvm/test/CodeGen/PowerPC/aix32-crsave.mir
llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
llvm/test/CodeGen/PowerPC/alloca-crspill.ll
llvm/test/CodeGen/PowerPC/byval-agg-info.ll
llvm/test/CodeGen/PowerPC/frame_index_scavenging.mir
llvm/test/CodeGen/PowerPC/mflr-store.mir
llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
llvm/test/CodeGen/RISCV/live-sp.mir
llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
llvm/test/CodeGen/RISCV/pr53662.mir
llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir
llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
llvm/test/CodeGen/RISCV/rvv/vxrm.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
llvm/test/CodeGen/RISCV/stack-inst-compress.mir
llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir
llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir
llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
llvm/test/CodeGen/RISCV/zdinx-spill.ll
llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir
llvm/test/CodeGen/RISCV/zilsd-spill.ll
llvm/test/CodeGen/SystemZ/frame-26.mir
llvm/test/CodeGen/SystemZ/frame-27.mir
llvm/test/CodeGen/SystemZ/frame-28.mir
llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir
llvm/test/CodeGen/SystemZ/tls-11.mir
llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
llvm/test/CodeGen/Thumb2/scavenge-lr.mir
llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
llvm/test/CodeGen/X86/cfi-xmm.ll
llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
llvm/test/CodeGen/X86/ipra-inline-asm.ll
llvm/test/CodeGen/X86/ipra-reg-usage.ll
llvm/test/CodeGen/X86/prologepilog_deref_size.mir
llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir
llvm/test/CodeGen/X86/push-cfi.ll
llvm/test/CodeGen/X86/throws-cfi-fp.ll
llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir
llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
llvm/test/DebugInfo/X86/prolog-params.mir
llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml
llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml
llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
llvm/test/tools/llvm-remarkutil/convert.test
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-1-instr-1-stack.yaml
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/1-func-2-instr-2-stack.yaml
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/2-identical-func-1-instr-1-stack.yaml
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/inconvertible-integer.yaml
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/no-instruction-count-remarks.yaml
llvm/test/tools/llvm-remarkutil/size-diff/Inputs/unexpected-key.yaml
llvm/tools/llvm-exegesis/lib/Assembler.cpp
llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
Removed:
################################################################################
diff --git a/flang/test/Driver/fsave-optimization-record.f90 b/flang/test/Driver/fsave-optimization-record.f90
index c039a1495dacc..6994fc628f167 100644
--- a/flang/test/Driver/fsave-optimization-record.f90
+++ b/flang/test/Driver/fsave-optimization-record.f90
@@ -41,7 +41,7 @@
! YAML: "-opt-record-format" "yaml"
! CHECK: --- !Analysis
-! CHECK: Pass: prologepilog
+! CHECK: Pass: prolog-epilog
! CHECK: Name: StackSize
! CHECK: Function: _QQmain
! CHECK: Pass: asm-printer
diff --git a/lld/test/ELF/lto/stats-file-option.ll b/lld/test/ELF/lto/stats-file-option.ll
index b1de6301b6695..4a22e00171e84 100644
--- a/lld/test/ELF/lto/stats-file-option.ll
+++ b/lld/test/ELF/lto/stats-file-option.ll
@@ -9,7 +9,7 @@
; CHECK: {
; CHECK: "asm-printer.EmittedInsts":
; CHECK: "inline.NumInlined":
-; CHECK: "prologepilog.NumFuncSeen":
+; CHECK: "prolog-epilog.NumFuncSeen":
; CHECK: }
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/docs/Remarks.rst b/llvm/docs/Remarks.rst
index 67ed94d9740f4..a22e8c30dfa30 100644
--- a/llvm/docs/Remarks.rst
+++ b/llvm/docs/Remarks.rst
@@ -442,12 +442,12 @@ Output statistics about the optimization remarks in the input set.
Top 10 remarks by pass:
inline 33%
asm-printer 33%
- prologepilog 33%
+ prolog-epilog 33%
Top 10 remarks:
asm-printer/InstructionCount 33%
inline/NoDefinition 33%
- prologepilog/StackSize 33%
+ prolog-epilog/StackSize 33%
opt-
diff .py
-----------
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index a37deee1e5ff9..0a6f19fdf24d7 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -247,7 +247,7 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
-DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass)
+DUMMY_MACHINE_FUNCTION_PASS("prolog-epilog-code", PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index d9557a3958978..54a77524add94 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -67,7 +67,7 @@
using namespace llvm;
-#define DEBUG_TYPE "prologepilog"
+#define DEBUG_TYPE "prolog-epilog"
using MBBVector = SmallVector<MachineBasicBlock *, 4>;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir b/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
index 434a0e3c82a1d..79478ee843604 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=prolog-epilog %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64 -passes='prolog-epilog' %s -o - | FileCheck %s
--- |
define i32 @_Z4funcv() {
diff --git a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
index 15b8e759dec42..b684896ff700a 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
# The tests below test the allocation of 128bit callee-saves
# on the stack, specifically their offsets.
diff --git a/llvm/test/CodeGen/AArch64/addg_subg.mir b/llvm/test/CodeGen/AArch64/addg_subg.mir
index 2a1ea4b723a7e..11a40a2f5b807 100644
--- a/llvm/test/CodeGen/AArch64/addg_subg.mir
+++ b/llvm/test/CodeGen/AArch64/addg_subg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog,aarch64-expand-pseudo %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prolog-epilog,aarch64-expand-pseudo %s -o - | FileCheck %s
# CHECK: renamable $x8 = IRG $sp, $xzr
diff --git a/llvm/test/CodeGen/AArch64/cfi_restore.mir b/llvm/test/CodeGen/AArch64/cfi_restore.mir
index a68cdeb492804..07a07bb1159ab 100644
--- a/llvm/test/CodeGen/AArch64/cfi_restore.mir
+++ b/llvm/test/CodeGen/AArch64/cfi_restore.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-- -start-after prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -start-after prolog-epilog -o - %s | FileCheck %s
---
name: fun
# CHECK: .cfi_startproc
diff --git a/llvm/test/CodeGen/AArch64/chkstk.ll b/llvm/test/CodeGen/AArch64/chkstk.ll
index ea4c486aecaef..8a3dea9807a78 100644
--- a/llvm/test/CodeGen/AArch64/chkstk.ll
+++ b/llvm/test/CodeGen/AArch64/chkstk.ll
@@ -2,12 +2,12 @@
; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
; RUN: llc -mtriple=aarch64-w64-mingw32 -verify-machineinstrs %s -o - \
; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
-; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog \
+; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prolog-epilog \
; RUN: | FileCheck -check-prefix CHECK-REGSTATE %s
; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs -code-model=large %s -o - \
; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
-; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog -code-model=large \
+; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prolog-epilog -code-model=large \
; RUN: | FileCheck -check-prefix CHECK-REGSTATE-LARGE %s
define void @check_watermark() {
diff --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
index 7fd0cee068fd1..0551857cbc839 100644
--- a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
+++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s
+# RUN: llc -o %t -filetype=obj -start-before=prolog-epilog %s
# RUN: llvm-dwarfdump --name="z0" %t | FileCheck %s --check-prefix=CHECKZ0
# RUN: llvm-dwarfdump --name="z1" %t | FileCheck %s --check-prefix=CHECKZ1
# RUN: llvm-dwarfdump --name="p0" %t | FileCheck %s --check-prefix=CHECKP0
diff --git a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
index 41ba5542150ab..029a695d4c983 100644
--- a/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
+++ b/llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s
+# RUN: llc -o %t -filetype=obj -start-before=prolog-epilog %s
# RUN: llvm-dwarfdump --name="value0" %t | FileCheck %s --check-prefix=CHECK0
# RUN: llvm-dwarfdump --name="value1" %t | FileCheck %s --check-prefix=CHECK1
# RUN: llvm-dwarfdump --name="value2" %t | FileCheck %s --check-prefix=CHECK2
diff --git a/llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir b/llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
index 4d651138465a1..474c835a12906 100644
--- a/llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
+++ b/llvm/test/CodeGen/AArch64/emit-prologue-clobber-verification.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o -
+# RUN: not --crash llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o -
#
# REQUIRES: asserts
#
diff --git a/llvm/test/CodeGen/AArch64/extra-callee-save.mir b/llvm/test/CodeGen/AArch64/extra-callee-save.mir
index f03dec0593845..61958914bb4b6 100644
--- a/llvm/test/CodeGen/AArch64/extra-callee-save.mir
+++ b/llvm/test/CodeGen/AArch64/extra-callee-save.mir
@@ -1,4 +1,4 @@
-#RUN: llc -mtriple=aarch64-- -run-pass prologepilog %s -o - | FileCheck %s
+#RUN: llc -mtriple=aarch64-- -run-pass prolog-epilog %s -o - | FileCheck %s
# Check that we spill a scratch register, but not also an additional
# emergency spill slot.
---
diff --git a/llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir b/llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
index a6236bd917129..b17515722758b 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-fpr128-spill.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-windows-msvc -run-pass=prologepilog %s -o - | FileCheck %s --check-prefix=CHECK-WINDOWS
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-windows-msvc -run-pass=prolog-epilog %s -o - | FileCheck %s --check-prefix=CHECK-WINDOWS
--- |
; Tests Q8 is assigned a 16-byte aligned offset after X10 is assigned an offset.
diff --git a/llvm/test/CodeGen/AArch64/framelayout-frame-record.mir b/llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
index 982a884730c75..4b7fff98f7c08 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -start-before prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -start-before prolog-epilog %s -o - | FileCheck %s
---
name: TestFrameRecordLocation
diff --git a/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir b/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
index 59b04dd5052fd..c1e6c2d84666b 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
---
name: framelayout_offset_immediate_change
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
index 5a75f540c60f6..d182dae3b40dd 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot-stack-hazard.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-stack-hazard-size=1024 -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-stack-hazard-size=1024 -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
define void @stack_hazard_streaming_compat() "aarch64_pstate_sm_compatible" { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
index 17ae97ba58077..5cf794e44a0cd 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
---
# This test verifies that the emergency scavenging slot is located near
# the SP when the stack is realigned.
diff --git a/llvm/test/CodeGen/AArch64/framelayout-split-sve.mir b/llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
index bb7ffb47d8dfe..21dd31f8e9ce7 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-split-sve.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -start-before=prologepilog %s -o - | FileCheck %s --check-prefix=ASM
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -start-before=prologepilog %s -filetype=obj -o %t
+# RUN: llc -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -start-before=prolog-epilog %s -o - | FileCheck %s --check-prefix=ASM
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -start-before=prolog-epilog %s -filetype=obj -o %t
# RUN: llvm-objdump --dwarf=frames %t | FileCheck %s --check-prefix=UNWINDINFO
# RUN: rm -rf %t
#
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
index 26b7ca3bf8c07..e794fe83c59a4 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
define void @hasBasepointer() #0 { ret void }
define void @hasBasepointer_sme_streaming() #1 { ret void }
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
index a7bde2a9f1c92..ec3bfa94a9b7e 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prolog-epilog %s -o - | FileCheck %s
--- |
define aarch64_sve_vector_pcs void @fix_restorepoint_p4() uwtable { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
index 35fd7ca77d5cf..57eaaa6b5094f 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prolog-epilog %s -o - | FileCheck %s
--- |
define aarch64_sve_vector_pcs void @access_large_stack() nounwind { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
index 680f9c335c250..0a979aa43de92 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog -mattr=+sve %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog -mattr=+sve %s -o - | FileCheck %s
---
# This test verifies that the emergency scavenging slot is located near the SP/BP.
name: LateScavengingSlot
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-win.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
index 0d84fa14d8672..d4a64c8bc9dc9 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-win.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --print-fixed-stack --version 5
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 --print-fixed-stack
-# RUN: llc -mattr=+sve -mtriple=aarch64-windows-msvc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mattr=+sve -mtriple=aarch64-windows-msvc -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve.mir b/llvm/test/CodeGen/AArch64/framelayout-sve.mir
index 110141609a59e..f0ae337df925d 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prologepilog %s -o - | FileCheck %s --check-prefix=ASM
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prologepilog %s -filetype=obj -o %t
+# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prolog-epilog %s -o - | FileCheck %s --check-prefix=ASM
+# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prolog-epilog %s -filetype=obj -o %t
# RUN: llvm-objdump --dwarf=frames %t | FileCheck %s --check-prefix=UNWINDINFO
# RUN: rm -rf %t
#
diff --git a/llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir b/llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
index bae954a7ad3d8..78d8371b2e9dd 100644
--- a/llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
+++ b/llvm/test/CodeGen/AArch64/large-stack-offset-calcs.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=arm64-apple-ios -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=prolog-epilog %s -o - | FileCheck %s
---
name: large_stack_offset_calc
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
index 1e14e7149817a..fa1da262fbd39 100644
--- a/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
+++ b/llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir
@@ -1,4 +1,4 @@
-# RUN: llc -start-before=prologepilog -stop-after=livedebugvalues -mattr=+sve -o - %s | FileCheck %s
+# RUN: llc -start-before=prolog-epilog -stop-after=livedebugvalues -mattr=+sve -o - %s | FileCheck %s
#
# FIXME: re-enable this run line when InstrRef LiveDebugValues is able to
# rely on the target spill/restore inst recognisers.
diff --git a/llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll b/llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
index 09107860c802b..b3c0c1b7c0beb 100644
--- a/llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
+++ b/llvm/test/CodeGen/AArch64/lr-reserved-for-ra-live-in.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -stop-after=prologepilog -simplify-mir -o - %s | FileCheck %s
+; RUN: llc -stop-after=prolog-epilog -simplify-mir -o - %s | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64e-apple-ios18.0"
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-bti.mir b/llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
index 177954fb5ade4..6885be5eccda2 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--- -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
# AArch64 Branch Target Enforcement treats the BR and BLR indirect branch
# instructions
diff erently. The BLR instruction can only target a BTI C
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
index ea995b002e976..eb858d532c51c 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - -debugify-and-strip-all-safe | FileCheck %s
-# RUN: llc -mtriple=aarch64-pc-windows-msvc -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=WINDOWS
+# RUN: llc -mtriple=aarch64--- -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--- -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - -debugify-and-strip-all-safe | FileCheck %s
+# RUN: llc -mtriple=aarch64-pc-windows-msvc -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=WINDOWS
--- |
define void @baz() #0 {
ret void
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir b/llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
index d935cebf2b069..48b9e07a4a253 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-no-noreturn-no-stack.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=arm64-apple-ios -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
# Noreturn functions conservatively need to save and restore lr.
# When there is no available register, the stack is used at call site.
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir b/llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
index f926040f3932d..221d17ad1191f 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-noreturn-no-stack.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=arm64-apple-ios -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
# Noreturn functions conservatively need to save and restore lr.
# When there is no available register, the stack is used at call site.
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir b/llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
index facd73dbe4cd7..91b8ecfdb9bdc 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-regsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prologepilog \
+# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prolog-epilog \
# RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s
# Check that we save LR to a callee-saved register when possible.
# foo() should use a callee-saved register. However, bar() should not.
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
index 9a983cbd6714e..5d5a8bc9c1a21 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=prologepilog -run-pass=machine-outliner \
+# RUN: llc -mtriple=aarch64 -run-pass=prolog-epilog -run-pass=machine-outliner \
# RUN: -verify-machineinstrs -run-pass=aarch64-ptrauth %s -o - | FileCheck %s
# Check that we save LR to a callee-saved register when possible.
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir b/llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
index 51dda1677a51b..ef50534b21c6b 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-size-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prologepilog \
+# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prolog-epilog \
# RUN: -run-pass=machine-outliner %s -pass-remarks-analysis='size-info' \
# RUN: -pass-remarks-output=%t.yaml -o /dev/null < %s 2> %t; \
# RUN: cat %t %t.yaml | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner.mir b/llvm/test/CodeGen/AArch64/machine-outliner.mir
index 66779addaff0a..03e3b21e886ba 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--- -run-pass=prologepilog -run-pass=machine-outliner -verify-machineinstrs -frame-pointer=non-leaf -outliner-leaf-descendants=false %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64--- -run-pass=prolog-epilog -run-pass=machine-outliner -verify-machineinstrs -frame-pointer=non-leaf -outliner-leaf-descendants=false %s -o - | FileCheck %s
--- |
@x = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir b/llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
index b6a573740d442..b7e66bd4434e4 100644
--- a/llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
+++ b/llvm/test/CodeGen/AArch64/memtag-stg-loop-reg-pressure.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prolog-epilog %s -verify-machineinstrs -o - | FileCheck %s
# This test ensures that when register pressure is extremely high, the compiler
# does not attempt to merge ST2Gi instructions into an STGloop. STGloop requires
diff --git a/llvm/test/CodeGen/AArch64/no-xzr-liveins.mir b/llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
index ef774b7de23d1..201236994a5cb 100644
--- a/llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
+++ b/llvm/test/CodeGen/AArch64/no-xzr-liveins.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-unknown-fuchsia -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-unknown-fuchsia -run-pass=prolog-epilog %s -o - | FileCheck %s
# This test ensures that constant registers like XZR are not considered live
# even if they are in the liveins list. This prevents the stack probe from
diff --git a/llvm/test/CodeGen/AArch64/pr157252.mir b/llvm/test/CodeGen/AArch64/pr157252.mir
index 319e54f0fa7e9..ca7cb72643159 100644
--- a/llvm/test/CodeGen/AArch64/pr157252.mir
+++ b/llvm/test/CodeGen/AArch64/pr157252.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass prologepilog -frame-pointer=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass prolog-epilog -frame-pointer=none -o - %s | FileCheck %s
---
name: test_addsxri_scalable_offset
stack:
diff --git a/llvm/test/CodeGen/AArch64/preserve.ll b/llvm/test/CodeGen/AArch64/preserve.ll
index 49fb3685bcfc1..596910e715f7a 100644
--- a/llvm/test/CodeGen/AArch64/preserve.ll
+++ b/llvm/test/CodeGen/AArch64/preserve.ll
@@ -1,7 +1,7 @@
; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
-; RUN: llc -stop-after=prologepilog -o - %s \
+; RUN: llc -stop-after=prolog-epilog -o - %s \
; RUN: | llc -x=mir -enable-ipra -passes="require<reg-usage>,function(machine-function(reg-usage-propagation,reg-usage-collector)),print<reg-usage>" -o /dev/null 2>&1 \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir b/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
index 223719d44d169..458d8f85b05d3 100644
--- a/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
+++ b/llvm/test/CodeGen/AArch64/prologue-epilogue-remarks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=prologepilog -pass-remarks-output=%t -pass-remarks-analysis=prologepilog -o /dev/null %s 2>&1
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=prolog-epilog -pass-remarks-output=%t -pass-remarks-analysis=prolog-epilog -o /dev/null %s 2>&1
# RUN: cat %t | FileCheck %s
...
---
@@ -6,7 +6,7 @@ name: fun0
stack:
- { id: 0, type: default, offset: 0, size: 8, alignment: 4 }
# CHECK-LABEL: --- !Analysis
-# CHECK-NEXT: Pass: prologepilog
+# CHECK-NEXT: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK: Function: fun0
# CHECK-NEXT: Args:
@@ -26,7 +26,7 @@ name: fun1
stack:
- { id: 0, type: default, offset: 0, size: 19, alignment: 4 }
# CHECK-LABEL: --- !Analysis
-# CHECK-NEXT: Pass: prologepilog
+# CHECK-NEXT: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK: Function: fun1
# CHECK-NEXT: Args:
@@ -46,7 +46,7 @@ name: fun2
stack:
- { id: 0, type: default, offset: 0, size: 1024, alignment: 4 }
# CHECK-LABEL: --- !Analysis
-# CHECK: Pass: prologepilog
+# CHECK: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK: Function: fun2
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir b/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
index 3db69cfb21593..5e7a0f978d29c 100644
--- a/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
+++ b/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/reloc-specifiers.mir b/llvm/test/CodeGen/AArch64/reloc-specifiers.mir
index 3c56874e441ab..f6aa5b4b4a295 100644
--- a/llvm/test/CodeGen/AArch64/reloc-specifiers.mir
+++ b/llvm/test/CodeGen/AArch64/reloc-specifiers.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=arm64-windows -start-after=prologepilog -show-mc-encoding \
+# RUN: llc -mtriple=arm64-windows -start-after=prolog-epilog -show-mc-encoding \
# RUN: -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AArch64/settag-merge.mir b/llvm/test/CodeGen/AArch64/settag-merge.mir
index 1eb23ef9cba75..a8d1dbbf98bec 100644
--- a/llvm/test/CodeGen/AArch64/settag-merge.mir
+++ b/llvm/test/CodeGen/AArch64/settag-merge.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
declare void @llvm.aarch64.settag(ptr nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
diff --git a/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir b/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
index f6fc627ac2d3d..e83817f0f123e 100644
--- a/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
+++ b/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
# Ensure references to scavenged stack slots in the CSR area use the
# FP as a base when the stack pointer must be aligned to something
diff --git a/llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir b/llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
index 6e448e68f4ab8..c0493f80a534a 100644
--- a/llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
+++ b/llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -start-before=localstackalloc -stop-after=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -start-before=localstackalloc -stop-after=prolog-epilog -o - %s | FileCheck %s
--- |
@__stack_chk_guard = external global ptr
diff --git a/llvm/test/CodeGen/AArch64/stack-guard-reassign.mir b/llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
index 6a7ef800b3d53..26804025127b3 100644
--- a/llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
+++ b/llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=arm64-apple-ios -start-before=localstackalloc -stop-after=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=arm64-apple-ios -start-before=localstackalloc -stop-after=prolog-epilog -o - %s | FileCheck %s
--- |
@__stack_chk_guard = external global ptr
diff --git a/llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir b/llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
index 56a3d280e0098..ac603c73f5992 100644
--- a/llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
+++ b/llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
...
# Ensure that objects with StackID > 0 are not allocated on the default stack
# (will not be allocated an offset) and are not considered in the calculation of
diff --git a/llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir b/llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
index 69b9ce9faf164..3d9c98827f077 100644
--- a/llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
+++ b/llvm/test/CodeGen/AArch64/stack-id-stackslot-scavenging.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-none-linux-gnu -start-before=greedy -stop-after=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -start-before=greedy -stop-after=prolog-epilog %s -o - | FileCheck %s
...
# Ensure that an object with a
diff erent stack-id is not allocated to a
# callee-save slot using stack-slot scavenging. This test saves X28 which
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
index b79890cc4a63e..bed882568b78c 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog %s -o - | FileCheck %s
# Regression test for a crash when the probing instruction
# to replace is last in the block.
--- |
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir b/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
index 0ba3f1515b636..fedb610ac5163 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-no-scratch-reg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc %s --start-before=shrink-wrap -stop-after=prologepilog -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc %s --start-before=shrink-wrap -stop-after=prolog-epilog -verify-machineinstrs -o - | FileCheck %s
--- |
target triple = "aarch64-linux"
diff --git a/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir b/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
index 470c7281f594b..9abd28fa3b4c7 100644
--- a/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
+++ b/llvm/test/CodeGen/AArch64/stack-probing-shrink-wrap.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc %s --start-before=shrink-wrap --stop-after=prologepilog -o - | FileCheck %s
+# RUN: llc %s --start-before=shrink-wrap --stop-after=prolog-epilog -o - | FileCheck %s
--- |
target triple = "aarch64-linux"
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir b/llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
index bcd716c5c8d6c..8732893cbb859 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
index 0fa5103232a89..02e1e37f26898 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-unknown-none-elf"
diff --git a/llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll b/llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
index 00a1fa747d77e..e5db57b9165e6 100644
--- a/llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
+++ b/llvm/test/CodeGen/AArch64/statepoint-call-lowering-lr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-none-linux-gnu -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s
+; RUN: llc -mtriple aarch64-none-linux-gnu -verify-machineinstrs -stop-after=prolog-epilog < %s | FileCheck %s
; Check that STATEPOINT instruction has an early clobber implicit def for LR.
target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll b/llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
index 05b504f5635a5..75ee777497b92 100644
--- a/llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
+++ b/llvm/test/CodeGen/AArch64/statepoint-call-lowering-sp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64-none-linux-gnu -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s
+; RUN: llc -mtriple aarch64-none-linux-gnu -verify-machineinstrs -stop-after=prolog-epilog < %s | FileCheck %s
; Check that STATEPOINT instruction prefer to use sp in presense of fp.
target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/sve-calling-convention.ll b/llvm/test/CodeGen/AArch64/sve-calling-convention.ll
index c3f7e9f28ebc2..3063e125037f6 100644
--- a/llvm/test/CodeGen/AArch64/sve-calling-convention.ll
+++ b/llvm/test/CodeGen/AArch64/sve-calling-convention.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=DARWIN
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR
-; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=prologepilog < %s | FileCheck %s --check-prefix=CHECKCSR
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=prolog-epilog < %s | FileCheck %s --check-prefix=CHECKCSR
+; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+sve -stop-after=prolog-epilog < %s | FileCheck %s --check-prefix=CHECKCSR
; CHECK-LABEL: name: nosve_signature
; DARWIN-LABEL: name: nosve_signature
diff --git a/llvm/test/CodeGen/AArch64/sve-ld1r.mir b/llvm/test/CodeGen/AArch64/sve-ld1r.mir
index a51dd0814db37..d673cca1a7e78 100644
--- a/llvm/test/CodeGen/AArch64/sve-ld1r.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ld1r.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that prologepilog works for each of the LD1R instructions for stack-based objects.
#
diff --git a/llvm/test/CodeGen/AArch64/sve-ldN.mir b/llvm/test/CodeGen/AArch64/sve-ldN.mir
index b6b89abc61bfc..7cd00b1ecda1e 100644
--- a/llvm/test/CodeGen/AArch64/sve-ldN.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ldN.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
--- |
define void @testcase_valid_offset() nounwind { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/sve-ldnf1.mir b/llvm/test/CodeGen/AArch64/sve-ldnf1.mir
index 2a7e8a43c6dcb..083e501242f2e 100644
--- a/llvm/test/CodeGen/AArch64/sve-ldnf1.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ldnf1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that prologepilog works for each of the LDNF1 instructions for stack-based objects.
#
diff --git a/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir b/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
index 1213914f80baa..021af943015a6 100644
--- a/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ldst-multi-vec.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -start-before=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -start-before=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
--- |
define void @testcase_valid_offset() "aarch64_pstate_sm_enabled" nounwind { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/sve-ldstnt1.mir b/llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
index 863d4d1975e44..169d351c10d22 100644
--- a/llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
+++ b/llvm/test/CodeGen/AArch64/sve-ldstnt1.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that prologepilog works for each of the LDNT1/STNT1 instructions for stack-based objects.
#
diff --git a/llvm/test/CodeGen/AArch64/sve-stN.mir b/llvm/test/CodeGen/AArch64/sve-stN.mir
index 7371f30a4a512..936e778e12fee 100644
--- a/llvm/test/CodeGen/AArch64/sve-stN.mir
+++ b/llvm/test/CodeGen/AArch64/sve-stN.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -start-before=prolog-epilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-OFFSET
--- |
define void @testcase_valid_offset() nounwind { entry: unreachable }
diff --git a/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir b/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
index b7b2e282e563e..31a15cce66212 100644
--- a/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
+++ b/llvm/test/CodeGen/AArch64/unreachable-emergency-spill-slot.mir
@@ -1,4 +1,4 @@
-#RUN: llc -mtriple=aarch64-- -run-pass prologepilog %s -o - | FileCheck %s
+#RUN: llc -mtriple=aarch64-- -run-pass prolog-epilog %s -o - | FileCheck %s
# Check that we use the frame pointer to address the emergency spill slot.
# Using the base pointer will result in an assert with "Emergency spill slot is
# out of reach".
diff --git a/llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir b/llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
index 7faab8c45aa7a..863537a997300 100644
--- a/llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
+++ b/llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass=regallocfast,prologepilog -simplify-mir -o - %s | FileCheck %s
+# RUN: llc -run-pass=regallocfast,prolog-epilog -simplify-mir -o - %s | FileCheck %s
# This test checks that the MIRParser correctly clobbers the registers
# that are not preserved by the unwinder (when the MIR contains an EH pad).
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir b/llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
index ebe3c41b68c1e..2987c33e75787 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame-predecrement.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check that the callee-saved registers are saved starting with a STP
# with predecrement, followed by a separate stack adjustment later,
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir b/llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
index e0e367668213e..4979e8e797c2d 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check where the stack variable is placed
# CHECK: - { id: 0, name: '', type: default, offset: -4, size: 4, alignment: 4,
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame0.mir b/llvm/test/CodeGen/AArch64/wineh-frame0.mir
index 9abc8699fd951..4d5eab29a1a70 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame0.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame0.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check save_regp_x, save_regp
# CHECK: early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -10
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame1.mir b/llvm/test/CodeGen/AArch64/wineh-frame1.mir
index 531ca14ee67ec..1cbff8fbb448e 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame1.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame1.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check save_fregp_x, save_fregp
# CHECK: early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -14
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame2.mir b/llvm/test/CodeGen/AArch64/wineh-frame2.mir
index 1c8cb1e79a998..dec3c714b7ddd 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame2.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame2.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check save_freg_x, save_frep, save_reg
# CHECK: early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -48
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame3.mir b/llvm/test/CodeGen/AArch64/wineh-frame3.mir
index c9a393144bc67..ea2c660babda1 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame3.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame3.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check save_reg_x, save_reg
# CHECK: early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -16
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame4.mir b/llvm/test/CodeGen/AArch64/wineh-frame4.mir
index 75dc37d4bd734..feab80b1cc9b9 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame4.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame4.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check save_freg_x, save_freg
# CHECK: early-clobber $sp = frame-setup STRDpre killed $d8, $sp, -16
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame5.mir b/llvm/test/CodeGen/AArch64/wineh-frame5.mir
index 32580f4f3f41c..42c42c06a36a0 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame5.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame5.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check multiple epilogues, save_reg, save_reg_x.
# CHECK-LABEL: bb.0.entry:
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame6.mir b/llvm/test/CodeGen/AArch64/wineh-frame6.mir
index d76fae1aad3dc..490495598a356 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame6.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame6.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Test that stack probe results in Nop unwind codes in the prologue. Test
# save_fplr, save_reg_x and stack_alloc with multiple updates
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame7.mir b/llvm/test/CodeGen/AArch64/wineh-frame7.mir
index d4e71d94c7d73..5a5a5e62f6b72 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame7.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame7.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Test that stack probe results in Nop unwind codes in the prologue. Test
# save_fplr, save_reg_x and stack_alloc with multiple updates.
diff --git a/llvm/test/CodeGen/AArch64/wineh-frame8.mir b/llvm/test/CodeGen/AArch64/wineh-frame8.mir
index 56f92f230fcf6..5970b964b3a70 100644
--- a/llvm/test/CodeGen/AArch64/wineh-frame8.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-frame8.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Test that the frame lowering emits correct SEH updates for the case without
# a stack frame (e.g. no callee saved registers, no frame pointer, just locals)
diff --git a/llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir b/llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
index e70242638a0f0..d3ccf4735aa30 100644
--- a/llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-save-lrpair1.mir
@@ -1,6 +1,6 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
# RUN: | FileCheck --check-prefix=ASM %s
# Check that an odd callee-saved GPR is paired with lr
diff --git a/llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir b/llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
index a91340cb534af..1379f81362821 100644
--- a/llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-save-lrpair2.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check that when LR is paired with a GPR, we don't combine it into a
# predecrement that can't be described as a SEH opcode.
diff --git a/llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir b/llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
index a576380c09738..2109de65940b3 100644
--- a/llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
+++ b/llvm/test/CodeGen/AArch64/wineh-save-lrpair3.mir
@@ -1,5 +1,5 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prolog-epilog \
+# RUN: -stop-after=prolog-epilog | FileCheck %s
# Check that an unpaired register that is even isn't paired with lr.
diff --git a/llvm/test/CodeGen/AArch64/wineh1.mir b/llvm/test/CodeGen/AArch64/wineh1.mir
index 1ba551a0f04b1..244e05854e74f 100644
--- a/llvm/test/CodeGen/AArch64/wineh1.mir
+++ b/llvm/test/CodeGen/AArch64/wineh1.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog -filetype=obj \
# RUN: | llvm-readobj --unwind - | FileCheck %s
# RUN: llc -o - %s -mtriple=aarch64-windows -run-pass=aarch64-ldst-opt \
# RUN: | FileCheck %s --check-prefix=CHECK-LDSTOPT
@@ -7,7 +7,7 @@
# https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
# Also test the generated assembler SEH directives.
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=asm \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog -filetype=asm \
# RUN: | FileCheck %s --check-prefix=ASM
# We expect to see the following in the .xdata section:
diff --git a/llvm/test/CodeGen/AArch64/wineh2.mir b/llvm/test/CodeGen/AArch64/wineh2.mir
index 529a9823a1ad4..008f24a276dbd 100644
--- a/llvm/test/CodeGen/AArch64/wineh2.mir
+++ b/llvm/test/CodeGen/AArch64/wineh2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -filetype=obj | llvm-readobj --unwind - | FileCheck %s
# Test that the pre/post increment save of a flating point register is correct.
diff --git a/llvm/test/CodeGen/AArch64/wineh3.mir b/llvm/test/CodeGen/AArch64/wineh3.mir
index 7cc15badb6567..58c83332b3235 100644
--- a/llvm/test/CodeGen/AArch64/wineh3.mir
+++ b/llvm/test/CodeGen/AArch64/wineh3.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -filetype=obj | llvm-readobj --unwind - | FileCheck %s
# Test that the register pairing of both general purpose and floating point
# registers is correctly saved in the .xdata section, as well as the pre/post
diff --git a/llvm/test/CodeGen/AArch64/wineh4.mir b/llvm/test/CodeGen/AArch64/wineh4.mir
index bdac1c04fb0b8..871445c42f353 100644
--- a/llvm/test/CodeGen/AArch64/wineh4.mir
+++ b/llvm/test/CodeGen/AArch64/wineh4.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -disable-branch-fold -filetype=obj \
# RUN: | llvm-readobj --unwind - | FileCheck %s
# Check that identical multiple epilgoues are correctly shared in .xdata.
diff --git a/llvm/test/CodeGen/AArch64/wineh5.mir b/llvm/test/CodeGen/AArch64/wineh5.mir
index 1c09b7875d9f5..e5b7385fa194f 100644
--- a/llvm/test/CodeGen/AArch64/wineh5.mir
+++ b/llvm/test/CodeGen/AArch64/wineh5.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -filetype=obj | llvm-readobj --unwind - | FileCheck %s
# Check that that the large stack allocation is correctly represented in .xdata.
diff --git a/llvm/test/CodeGen/AArch64/wineh6.mir b/llvm/test/CodeGen/AArch64/wineh6.mir
index 098efe8da4535..55ae3b55c1e50 100644
--- a/llvm/test/CodeGen/AArch64/wineh6.mir
+++ b/llvm/test/CodeGen/AArch64/wineh6.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -filetype=obj | llvm-readobj --unwind - | FileCheck %s
# Check save_fplr_x, set_fp, alloc_s
diff --git a/llvm/test/CodeGen/AArch64/wineh7.mir b/llvm/test/CodeGen/AArch64/wineh7.mir
index 32d0ab805e4c7..a94dd94fa9225 100644
--- a/llvm/test/CodeGen/AArch64/wineh7.mir
+++ b/llvm/test/CodeGen/AArch64/wineh7.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -filetype=obj | llvm-readobj --unwind - | FileCheck %s
# Check AddFP
diff --git a/llvm/test/CodeGen/AArch64/wineh8.mir b/llvm/test/CodeGen/AArch64/wineh8.mir
index 4209b5bdf4c28..746b587ea534e 100644
--- a/llvm/test/CodeGen/AArch64/wineh8.mir
+++ b/llvm/test/CodeGen/AArch64/wineh8.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
+# RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prolog-epilog \
# RUN: -disable-branch-fold -filetype=obj \
# RUN: | llvm-readobj --unwind - | FileCheck %s
# Check that non-identical multiple epilgoues are correctly shared in .xdata.
diff --git a/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir b/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
index 52d0dffc20712..2c56c0675f71d 100644
--- a/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
+++ b/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
@@ -1,7 +1,7 @@
# RUN: llc -O2 -o - %s -mtriple=aarch64-windows -start-before=shrink-wrap \
-# RUN: -stop-after=prologepilog | FileCheck %s --check-prefix=WIN64
+# RUN: -stop-after=prolog-epilog | FileCheck %s --check-prefix=WIN64
# RUN: llc -O2 -o - %s -mtriple=aarch64-linux -start-before=shrink-wrap \
-# RUN: -stop-after=prologepilog | FileCheck %s --check-prefix=LINUX
+# RUN: -stop-after=prolog-epilog | FileCheck %s --check-prefix=LINUX
# This tests checks that shrink wrapping bails out on Windows AMR64 due to the
# use of Windows CFI. We don't currently support fragments for WIndows EH on
diff --git a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
index 8e1142474447e..cb4c92bd187ca 100644
--- a/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
+++ b/llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
@@ -1,4 +1,4 @@
-# RUN: llc -start-before=prologepilog -filetype=obj -o %t %s
+# RUN: llc -start-before=prolog-epilog -filetype=obj -o %t %s
# RUN: llvm-dwarfdump --name=obj1 %t | FileCheck %s --check-prefix=CHECKDWARF1
# RUN: llvm-dwarfdump --name=obj2 %t | FileCheck %s --check-prefix=CHECKDWARF2
# RUN: llvm-objdump --no-print-imm-hex -d %t | FileCheck %s --check-prefix=CHECKASM
diff --git a/llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir b/llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
index 350e2c58f222d..0f80268fd6345 100644
--- a/llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
+++ b/llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -run-pass=prolog-epilog -o - %s | FileCheck %s
# On PAL, we need to ensure SRSRC do not clobber GIT pointer, passed
# in SGPR8 for HS or GS
diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
index ac52ca7012561..026076f706a86 100644
--- a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX908 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX908 %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes='prolog-epilog' %s -o - | FileCheck -check-prefix=GFX908 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX90A %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes='prolog-epilog' %s -o - | FileCheck -check-prefix=GFX90A %s
-# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX908-FLATSCR %s
+# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX908-FLATSCR %s
# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes='prolog-epilog' %s -o - | FileCheck -check-prefix=GFX908-FLATSCR %s
-# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX90A-FLATSCR %s
+# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX90A-FLATSCR %s
# RUN: llc -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes='prolog-epilog' %s -o - | FileCheck -check-prefix=GFX90A-FLATSCR %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
index 7f26e413cf780..c674f9a988c26 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=prologepilog,postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX908 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=prolog-epilog,postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX908 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes='prolog-epilog,post-ra-pseudos' -o - %s | FileCheck -check-prefix=GFX908 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
index 60104a0756689..7876ccdeeb4f0 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass prologepilog,machine-cp -o - %s | FileCheck -check-prefix=GFX942 %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass prolog-epilog,machine-cp -o - %s | FileCheck -check-prefix=GFX942 %s
--- |
define amdgpu_kernel void @agpr_spill_copy() #0 { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
index 5016aa9c96f39..f7e702565dd17 100644
--- a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
+++ b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 %s -o - -run-pass prologepilog -verify-machineinstrs | FileCheck -check-prefix=GFX908-PEI %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 %s -o - -run-pass prologepilog,machine-cp -verify-machineinstrs | FileCheck -check-prefix=GFX908-PEI-MACHINECP %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 %s -o - -run-pass prolog-epilog -verify-machineinstrs | FileCheck -check-prefix=GFX908-PEI %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 %s -o - -run-pass prolog-epilog,machine-cp -verify-machineinstrs | FileCheck -check-prefix=GFX908-PEI-MACHINECP %s
# When VGPRs are available for spilling, prologepilog marks the tuple implicit-def as well as implicit in the first spill instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
index 23501793d3afd..0057d5560eba7 100644
--- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
+++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -start-before=greedy,1 -stop-after=prologepilog -verify-machineinstrs -verify-regalloc -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -start-before=greedy,1 -stop-after=prolog-epilog -verify-machineinstrs -verify-regalloc -o - %s | FileCheck --check-prefixes=GCN %s
# The VGPR pair spilled and restored around the callsite is used in the next basic block.
#
diff --git a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
index 7e6d841b7ec13..194f78b06613e 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-lower-sgpr-spills,greedy,si-lower-wwm-copies,virtregrewriter,prologepilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=si-lower-sgpr-spills,greedy,si-lower-wwm-copies,virtregrewriter,prolog-epilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
---
name: widget
diff --git a/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir b/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
index 1aa341b6c7dc0..6132c4ea3e61d 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=prologepilog %s -o - | FileCheck --check-prefix=GFX908 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -start-before=prologepilog %s -o - | FileCheck --check-prefix=GFX90A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX908 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -start-before=prolog-epilog %s -o - | FileCheck --check-prefix=GFX90A %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
index 209ac8e811456..c7aa1a1073a99 100644
--- a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
+++ b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx906 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s
# Make sure the modified CSR VGPRs are added as live-in to the entry
# block.
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
index 5132995428ef5..b0dd3d8e6fa2a 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir
@@ -1,13 +1,13 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
-
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
+
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
---
name: s_add_i32__inline_imm__fi_offset0
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
index 442018d21734a..7c591bca8cc7b 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir
@@ -1,13 +1,13 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
---
name: s_add_u32__inline_imm__fi_offset0
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
index e71ee5d40e05f..c87cb4af943f6 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX8 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX900 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX1010 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX1100 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX1200 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX900 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX1010 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX1100 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX1200 %s
---
name: s_copy_frame_index_elimination_failure_pei
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
index ba5945e840ba0..0e67d69123663 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir
@@ -1,13 +1,13 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
---
name: s_or_b32__inline_imm__fi_offset0
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
index f561ebf0615b0..da764d2b8fec6 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-scc-clobber.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUF %s
---
# S_CSELECT_B32 with a frame index true-operand, preceded immediately by
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
index 210040b8c3da9..a2c0306edecf5 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prolog-epilog -o - %s | FileCheck %s
# s_cselect_b32 does not allow vreg & should use the sreg frameindex generated
# by v_readfirstlane_b32 in eliminateFrameIndex.
---
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
index eab62340f29e5..cd0e12edd22e3 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# Test wave32
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=FLATSCRW32 %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
index 26f230f168127..6d0e8f691e9e2 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir
@@ -1,15 +1,15 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog -debugify-and-strip-all-safe %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX8 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX900 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX10 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog -debugify-and-strip-all-safe %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX7 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX900 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=MUBUFW64,GFX10 %s
# FIXME: Test in wave32
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX942 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX11 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX12 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX942 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX11 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=FLATSCRW64,GFX12 %s
---
name: v_add_co_u32_e32__inline_imm__fi_offset0
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
index 8a06215541d6c..bebd9764cb6e2 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUFW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
---
name: v_add_u32_e32__inline_imm__fi_offset0
diff --git a/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir b/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
index 1711c9710efdc..8e1212812e1a5 100644
--- a/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
+++ b/llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prolog-epilog -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll b/llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
index 2e998ddcfaa46..722e2b76dc60d 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=prologepilog < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=prolog-epilog < %s | FileCheck -check-prefix=GCN %s
; It is a small loop test that iterates over the array member of the structure argument passed byval to the function.
; The loop code will keep the prologue and epilogue blocks apart.
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
index e5955ad3d1d49..4db7ed3a9dc6f 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi-gfx1250.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=si-fold-operands -stop-after=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=si-fold-operands -stop-after=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
---
name: test_fold_fi_scratch_load_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir b/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
index e861a15981186..fcd2f2023e424 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GFX11 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GFX11 %s
...
---
name: tied_operand_test
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index.mir b/llvm/test/CodeGen/AMDGPU/frame-index.mir
index dae03b2ff860e..ba0871ab744e5 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index.mir
+++ b/llvm/test/CodeGen/AMDGPU/frame-index.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX8,GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX900,GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=GFX90A,GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX8,GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX900,GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=GFX90A,GCN %s
---
name: func_add_constant_to_fi_divergent_i32
diff --git a/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
index 43a7756f0aec4..cbf6f7850e60e 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
+++ b/llvm/test/CodeGen/AMDGPU/frame-lowering-entry-all-sgpr-used.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# CHECK-LABEL: all_sgpr_used
# CHECK: V_CMP_LT_U32_e64
diff --git a/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir b/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
index b2ba63cc5c14f..81589968a7dad 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
+++ b/llvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# CHECK-LABEL: name: foo
diff --git a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
index 1a9939bd4f2bc..3e429f7308072 100644
--- a/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-new-pm=1 -enable-ipra -print-regusage -filetype=null 2>&1 < %s | FileCheck %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=prologepilog -o - %s \
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -stop-after=prolog-epilog -o - %s \
; RUN: | llc -x=mir -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -filetype=null 2>&1 \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
index af3283df7e089..a23de7d937bee 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
+++ b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# Compiler used to assert when voffset field is enabled in the MUBUF instruction for a VGPR spill inside a kernel body
# when the frame pointer is enabled. That limitation is now removed and this test should compile without any crash.
diff --git a/llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll b/llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
index 966e5c8f460dc..535b9cda5667a 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-function-info-cwsr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -stop-after=prologepilog < %s | FileCheck -check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -stop-after=prolog-epilog < %s | FileCheck -check-prefix=CHECK %s
; Make sure we use a stack pointer and allocate 112 * 4 bytes at the beginning of the stack.
diff --git a/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir b/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
index e881d5851a4c8..d0104ca1f7639 100644
--- a/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
+++ b/llvm/test/CodeGen/AMDGPU/mcinstlower-external-symbol-reloc.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prologepilog %s -o - | FileCheck --check-prefix=ASM %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prologepilog -filetype=obj %s -o %t.o && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prolog-epilog %s -o - | FileCheck --check-prefix=ASM %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-after=prolog-epilog -filetype=obj %s -o %t.o && llvm-readobj -r %t.o | FileCheck --check-prefix=ELF %s
# AMDGPUMCInstLower must apply the operand's target flag specifier when
# lowering an MO_ExternalSymbol operand, just like it does for
diff --git a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
index 206f5acb5789a..60caecc0d47ee 100644
--- a/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
+++ b/llvm/test/CodeGen/AMDGPU/mir-print-dead-csr-fi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -run-pass=prolog-epilog -o - %s | FileCheck %s
# Make sure the MIR printer doesn't crash when there are dead frame indexes. The
# CSR SGPR frame indexes are inserted, but deleted.
diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
index a23d5dac49011..967f88d77d2b6 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --stop-after=greedy,2 < %s | FileCheck -check-prefix=REGALLOC-GFX908 %s
-;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --stop-after=prologepilog < %s | FileCheck -check-prefix=PEI-GFX908 %s
+;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 --stop-after=prolog-epilog < %s | FileCheck -check-prefix=PEI-GFX908 %s
;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 --stop-after=greedy,2 < %s | FileCheck -check-prefix=REGALLOC-GFX90A %s
-;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 --stop-after=prologepilog < %s | FileCheck -check-prefix=PEI-GFX90A %s
+;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 --stop-after=prolog-epilog < %s | FileCheck -check-prefix=PEI-GFX90A %s
; Partial reg copy and spill missed during regalloc handled later at frame lowering.
define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
index 5f46e4de24461..25fc7102d2dc9 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
--- |
declare amdgpu_cs_chain void @callee()
diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
index e0ed6a89f4821..a4661751a03e1 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
# We're keeping the IR around for the callees and the CCs
diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
index 8e0f0aac75f37..29ec5e3bff8c6 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
@@ -1,12 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A-V2A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A-V2A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A-V2A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A-V2A %s
---
name: test_spill_av_v1
diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
index bbe489138158e..27143dcd2a0fb 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck %s
# Test that the buildSpillLoadStore does correct calculations for Maxoffset in case of
# spill instructions. Must emit offset within 13 bit signed number range.
diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
index 4b25392aaa797..c822a03c86f8d 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
index 32a8082c012ad..69696f7814a58 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
@@ -1,12 +1,12 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A-V2A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=MUBUF-GFX90A-V2A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -mattr=+enable-flat-scratch -amdgpu-spill-vgpr-to-agpr=1 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=FLATSCR-GFX90A-V2A %s
---
name: test_spill_v1
diff --git a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
index adec09e663f43..4589d92a53144 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# The wrong form of scavengeRegister was used, so it wasn't accounting
# for the iterator passed to eliminateFrameIndex. It was instead using
diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
index 71e7ca11a86cd..80565c55e9266 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# Test what happens when an SGPR is unavailable for the unused add
# carry out when materializing the frame index.
diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
index 7c4e03fd0e6df..6a3ee3e4d12ac 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-gfx9.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog -mattr=+enable-flat-scratch %s -o - | FileCheck --check-prefix=FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck --check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog -mattr=+enable-flat-scratch %s -o - | FileCheck --check-prefix=FLATSCR %s
# Test what happens when an SGPR is unavailable for the unused add. The non-inline constant needs to be folded into the add instruction and not materialized in a register.
diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
index cd335321e2156..4e537c977576e 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck %s
# Frame virtual SGPRs should not be used, as the register scavenger cannot usefully spill them anymore.
# Spilling is also worse than increment and restore of a frame register. There should be no spills remaining.
diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
index 27a82d910c30d..d918e368027f1 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX9-FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX9-FLATSCR %s
# Test case where spilling a VGPR to an emergency slot is needed during frame index elimination.
diff --git a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
index 623bca7a976ad..47ca179fdd169 100644
--- a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
+++ b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W32
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W64
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W32
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W64
--- |
define void @one_block() #0 { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
index 37c8788d8d691..788f9579d2e17 100644
--- a/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
+++ b/llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
# The scratch register vgpr0 is used here to spill sgpr35 register.
# The function also returns a value that goes via. vgpr0.
diff --git a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
index f08ac3cb5ae33..4570cc4321478 100644
--- a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck %s
---
name: same_slot_agpr_sgpr
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
index 2f6c628d290ea..68dc53f9443f3 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck -check-prefix=PEI %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -verify-machineinstrs --start-before=si-lower-sgpr-spills --stop-after=prolog-epilog -o - %s | FileCheck -check-prefix=PEI %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=true -passes=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILL %s
# After handling the SGPR spill to VGPR in SILowerSGPRSpills pass, replace the dead frame index in the DBG_VALUE instruction with reg 0.
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
index 2e56dcad64840..3170f16b8248f 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=amdgcn-unknown-amdpal -mcpu=gfx1030 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs --stress-regalloc=5 -o - %s | FileCheck -check-prefix GCN %s
+# RUN: llc -mtriple=amdgcn-unknown-amdpal -mcpu=gfx1030 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs --stress-regalloc=5 -o - %s | FileCheck -check-prefix GCN %s
--- |
define amdgpu_gfx [13 x i32] @test_main() #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
index a11e50e1df0e2..db1042a74ca8a 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prologepilog %s -filetype=null 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prolog-epilog %s -filetype=null 2>&1 | FileCheck %s
# We have to keep SCC live at the point the spill is handled, but also
# need to manipulate exec since we don't have any free SGPRs to save
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
index 0b1b3e9ad254a..f6a06ff0daec1 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=VMEM-GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=VMEM-GFX8 %s
# Test that if we have a spill with a live SCC def, and we the offset
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
index 7d6218a406ce7..884806f0cf194 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=false -verify-machineinstrs -start-before=si-lower-sgpr-spills -stop-after=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-sgpr-to-vgpr=false -verify-machineinstrs -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -o - %s | FileCheck %s
# Check that we allocate 2 emergency stack slots if we're spilling
# SGPRs to memory and potentially have an offset larger than fits in
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
index 2c3d1a1810e60..104689902ee99 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN64-MUBUF %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN32-MUBUF %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-flat-scratch -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN64-FLATSCR %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -filetype=obj -verify-machineinstrs -start-before=prologepilog %s -filetype=null
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GCN64-MUBUF %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GCN32-MUBUF %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+enable-flat-scratch -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GCN64-FLATSCR %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -filetype=obj -verify-machineinstrs -start-before=prolog-epilog %s -filetype=null
# Check not crashing when emitting ISA
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
index f32664bd8f1ab..67dd79d0ccbfd 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=CHECK %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=CHECK %s
---
name: spill_a64_kill
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
index f25228f37f05b..f84d549d6efeb 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regallocfast -o - %s | FileCheck -check-prefix=GFX908-SPILLED %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=regallocfast -o - %s | FileCheck -check-prefix=GFX908-SPILLED %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regallocfast,prologepilog -o - %s | FileCheck -check-prefix=GFX908-EXPANDED %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=regallocfast,prolog-epilog -o - %s | FileCheck -check-prefix=GFX908-EXPANDED %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regallocfast -o - %s | FileCheck -check-prefix=GFX90A-SPILLED %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes=regallocfast -o - %s | FileCheck -check-prefix=GFX90A-SPILLED %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regallocfast,prologepilog -o - %s | FileCheck -check-prefix=GFX90A-EXPANDED %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=regallocfast,prolog-epilog -o - %s | FileCheck -check-prefix=GFX90A-EXPANDED %s
---
name: spill_restore_agpr32
diff --git a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
index deca1cfe73aab..fcaaf6ba82d62 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# Make sure the initial first $sgpr1 = COPY $sgpr2 copy is not deleted
# by the copy propagation after lowering the spill.
diff --git a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
index c7eaa4521e65f..6e0d6a2f2e077 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx950 -run-pass prologepilog,machine-cp -o - %s | FileCheck -check-prefix=GFX950 %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx950 -run-pass prolog-epilog,machine-cp -o - %s | FileCheck -check-prefix=GFX950 %s
--- |
define amdgpu_kernel void @full_copy() #0 { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
index cfa09c149e4c6..eec9fd11e067d 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=prologepilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=prolog-epilog -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# There are free scratch SGPRs available and hence use the smallest available pair for exec copy
# instead of the pair in the CSR range already given.
diff --git a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
index 30300aa8ec063..ff9541e4f43b7 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=GFX10 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=GFX11 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck --check-prefix=GFX9 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck --check-prefix=GFX10 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck --check-prefix=GFX11 %s
--- |
define amdgpu_kernel void @check_vcc() #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
index b59fa085b24db..5b597478d827b 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+enable-flat-scratch -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+enable-flat-scratch -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
---
name: partial_spill_v128_1_of_4
diff --git a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
index 52603cf725288..4ae6fb1554a99 100644
--- a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=EXPANDED %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
---
name: spill_restore_vgpr16
diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.mir b/llvm/test/CodeGen/AMDGPU/spillv16.mir
index 93a330d156e38..ad89eeeb50bdb 100644
--- a/llvm/test/CodeGen/AMDGPU/spillv16.mir
+++ b/llvm/test/CodeGen/AMDGPU/spillv16.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=regallocfast,prologepilog -o - %s | FileCheck -check-prefix=EXPANDED %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=regallocfast,prologepilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=regallocfast,prolog-epilog -o - %s | FileCheck -check-prefix=EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=regallocfast,prolog-epilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
---
name: spill_restore_vgpr16
diff --git a/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
index 6d70a2d057d62..96105caf164a8 100644
--- a/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
+++ b/llvm/test/CodeGen/AMDGPU/spillv16Kernel.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=EXPANDED %s
-# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=prologepilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=EXPANDED %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1250 -mattr=+real-true16 -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=SRAMECC-EXPANDED %s
--- |
define amdgpu_kernel void @spill_i16_alu() #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
index 933d5b228ecfa..9c0495309253c 100644
--- a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
+++ b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=prologepilog,machine-cp -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=prolog-epilog,machine-cp -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# The COPY that moves the return value to VGPR0 should not be removed during machine-cp. The spill restore of the same register that follows,
# meant to only reload its inactive lanes. By marking the reg itself as the tied-op in the spill reload prevents the undesired optimization.
diff --git a/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir b/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
index 5b330e892aa34..5f4d1fad74d77 100644
--- a/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
+++ b/llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# VGPR spill code in the prolog sets the `IsKill` flag for the spilled register
# based on the entry block's livein info.
diff --git a/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir b/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
index dd7d96f9d6e3c..604e5036626e3 100644
--- a/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog -mattr=+enable-flat-scratch %s -o - | FileCheck --check-prefix=FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck --check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog -mattr=+enable-flat-scratch %s -o - | FileCheck --check-prefix=FLATSCR %s
---
name: use_restore_frame_reg
diff --git a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
index ecbb1c4d5a112..41cf0833ca2f3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
+++ b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+enable-flat-scratch -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+enable-flat-scratch -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck -check-prefix=GCN %s
# A spilled register can be restored to its superclass during regalloc.
# As a result, we might see AGPR spills restored to VGPRs or the other way around.
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir b/llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
index 6ef1c33ed18f6..68b583abf47b1 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s
# The spill slot for the VGPR block needs to hold v40 and v43, so it needs to be
# 16 bytes large.
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
index 7c559f74f949a..9d06e8461e770 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck %s
# After handling the VGPR spill to AGPR copy, replace the dead frame index in the DBG_VALUE instruction with reg 0.
# Otherwise, the test would crash while trying to replace the dead frame index.
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
index 53629cdfb932b..2f3139c4a181b 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -run-pass=prolog-epilog -o - %s | FileCheck %s
--- |
define amdgpu_kernel void @test() { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
index 2058a94b0614a..9589afdfde3be 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -verify-machineinstrs -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -amdgpu-spill-vgpr-to-agpr=true -verify-machineinstrs -run-pass=prolog-epilog -o - %s | FileCheck %s
# After handling the VGPR spill to AGPR copy, we replace the dead frame index in the DBG_VALUE instruction with reg 0.
# Skip looking for frame indices in the debug value instruction for incoming arguments passed via stack. The test would crash otherwise.
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
index f91d23430b60f..87f9011f2146f 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUF %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX9-FLATSCR %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=prologepilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX10-FLATSCR %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=VMEM-GFX8 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=MUBUF %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=prolog-epilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX9-FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=prolog-epilog -mattr=+enable-flat-scratch %s -o - | FileCheck -check-prefix=GFX10-FLATSCR %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=VMEM-GFX8 %s
# Test that if we have a spill with a live SCC def, and the offset
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
index 0fba9b26c0458..151f48255a9ac 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX900 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX942 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX12,GFX1200 %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX12,GFX1250 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=CHECK,GFX900 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=CHECK,GFX942 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=CHECK,GFX12,GFX1200 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -run-pass=prolog-epilog %s -o - | FileCheck -check-prefixes=CHECK,GFX12,GFX1250 %s
---
name: spill_v32
diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
index 4fefdef6e1995..f86e0e832c67b 100644
--- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
+++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=prolog-epilog -o - %s | FileCheck %s
---
name: save_inactive_lanes_non_csr_vgpr
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
index 41d0029b7f1f1..7cb3939e994c3 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reg-shift-down-gfx11plus.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prolog-epilog %s -o - | FileCheck -check-prefix=GCN %s
---
name: wwm_reg_skip_sort_16bit
diff --git a/llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir b/llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
index 6a6d474fd283d..8b4e038453707 100644
--- a/llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
+++ b/llvm/test/CodeGen/ARM/execute-only-save-cpsr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog %s -o - | FileCheck %s
# Tests to check that CPSR is saved and restored if live when we emit tMOVi32imm
# to resolve a frame offset.
diff --git a/llvm/test/CodeGen/ARM/fpoffset_overflow.mir b/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
index 006acf68663aa..273228b070d2f 100644
--- a/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
+++ b/llvm/test/CodeGen/ARM/fpoffset_overflow.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prolog-epilog | FileCheck %s
---
# This should trigger an emergency spill in the register scavenger because the
# frame offset into the large argument is too large.
diff --git a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
index 9a557c506922a..0e299600d996d 100644
--- a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
+++ b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr-status-regs.mir
@@ -1,16 +1,16 @@
-# RUN: llc -mtriple=armv7-none-none-eabihf -mcpu=cortex-r5 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=armv7-none-none-eabihf -mcpu=cortex-r5 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-R-ARM %s
-# RUN: llc -mtriple=armv7-none-none-eabihf -mcpu=cortex-r4 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=armv7-none-none-eabihf -mcpu=cortex-r4 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-R-ARM %s
-# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-r5 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-r5 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-R-THUMB %s
-# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-r4 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-r4 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-R-THUMB %s
-# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-m3 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-m3 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-M-THUMB %s
-# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-m4 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv7-none-none-eabihf -mcpu=cortex-m4 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-M-THUMB %s
-# RUN: llc -mtriple=thumbv8-none-none-eabihf -mcpu=cortex-m33 -o - %s -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv8-none-none-eabihf -mcpu=cortex-m33 -o - %s -run-pass=prolog-epilog \
# RUN: | FileCheck --check-prefix=CHECK-M-THUMB %s
# =============================================================================
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
index 7634ecd6e863a..5923288f9002a 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
+++ b/llvm/test/CodeGen/ARM/machine-outliner-calls.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=arm-- -run-pass=prologepilog -run-pass=machine-outliner \
+# RUN: llc -mtriple=arm-- -run-pass=prolog-epilog -run-pass=machine-outliner \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
index e71edc8ceb3f6..c53a4157733ba 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
+++ b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-arm.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=armv7-- -run-pass=prologepilog -run-pass=machine-outliner \
+# RUN: llc -mtriple=armv7-- -run-pass=prolog-epilog -run-pass=machine-outliner \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
index f2cdaebdfa8ba..a31cf7ea035fe 100644
--- a/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
+++ b/llvm/test/CodeGen/ARM/machine-outliner-stack-fixup-thumb.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=thumbv7-- -run-pass=prologepilog \
+# RUN: llc -mtriple=thumbv7-- -run-pass=prolog-epilog \
# RUN: -run-pass=machine-outliner %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir b/llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
index 1e491a248cad5..864173000957f 100644
--- a/llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
+++ b/llvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog %s -o - | FileCheck %s
# Make sure we use the correct offset for stack accesses using the base pointer
# within call frame blocks. Key points of test:
diff --git a/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir b/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
index 07f12c0bc8cd8..897570c561ea2 100644
--- a/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
+++ b/llvm/test/CodeGen/ARM/noreturn-csr-skip.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple thumbv7m-none-eabi -run-pass prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple thumbv7m-none-eabi -run-pass prolog-epilog %s -o - | FileCheck %s
--- |
define void @throw() noreturn { unreachable }
diff --git a/llvm/test/CodeGen/ARM/pei-swiftself.mir b/llvm/test/CodeGen/ARM/pei-swiftself.mir
index f7b702f58e853..318c9938505d4 100644
--- a/llvm/test/CodeGen/ARM/pei-swiftself.mir
+++ b/llvm/test/CodeGen/ARM/pei-swiftself.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -mtriple=arm-- -run-pass prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=arm-- -run-pass prolog-epilog | FileCheck %s
--- |
define swiftcc ptr @need_emergency_slot(ptr swiftself %v) {
; Just a dummy to add a swiftself bit. The real code is in the MI below.
diff --git a/llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir b/llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
index a563fd244643d..98c80aeda31d0 100644
--- a/llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
+++ b/llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s
+# RUN: llc -o - %s -run-pass=prolog-epilog | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/ARM/stack_frame_offset.mir b/llvm/test/CodeGen/ARM/stack_frame_offset.mir
index 423928d8c6b6f..dffff9f95efa2 100644
--- a/llvm/test/CodeGen/ARM/stack_frame_offset.mir
+++ b/llvm/test/CodeGen/ARM/stack_frame_offset.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/llvm/test/CodeGen/ARM/tldrlit_ga_size.mir b/llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
index 189372aa110a2..6d9af9110ffbb 100644
--- a/llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
+++ b/llvm/test/CodeGen/ARM/tldrlit_ga_size.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog %s -o - | FileCheck %s
--- |
target triple = "thumbv5e-none-darwin"
diff --git a/llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll b/llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
index 88fe4ce24daf3..d939d34deaae8 100644
--- a/llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
+++ b/llvm/test/CodeGen/BPF/BTF/func-nocall-undef-dead-arg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=bpfel -mcpu=v3 -stop-after=prologepilog -o - %s | FileCheck -check-prefixes=MIR %s
+; RUN: llc -mtriple=bpfel -mcpu=v3 -stop-after=prolog-epilog -o - %s | FileCheck -check-prefixes=MIR %s
; RUN: llc -mtriple=bpfel -mcpu=v3 -filetype=obj -o %t1 %s
; RUN: llvm-objcopy --dump-section='.BTF'=%t2 %t1
; RUN: %python %p/print_btf.py %t2 | FileCheck -check-prefixes=BTF %s
diff --git a/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir b/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
index 2a6dbefb77a2a..2ab5ba37847dc 100644
--- a/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
+++ b/llvm/test/CodeGen/Hexagon/aligna-prologue-expansion.mir
@@ -1,6 +1,6 @@
-# RUN: llc -mtriple=hexagon -run-pass prologepilog %s -o - | FileCheck %s
-# RUN: llc -mtriple=hexagon -run-pass prologepilog -spill-func-threshold=0 %s -o - | FileCheck --check-prefix=SPILL-FUNC %s
-# RUN: llc -mtriple=hexagon -run-pass prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=hexagon -run-pass prolog-epilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=hexagon -run-pass prolog-epilog -spill-func-threshold=0 %s -o - | FileCheck --check-prefix=SPILL-FUNC %s
+# RUN: llc -mtriple=hexagon -run-pass prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify that PS_aligna is placed AFTER all CSR spills.
#
diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
index 4fa77a0b221b8..d988069dd501b 100644
--- a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
+++ b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=hexagon -verify-machineinstrs -run-pass prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=hexagon -verify-machineinstrs -run-pass prolog-epilog -o - %s | FileCheck %s
# The PS_vstorerw_ai of W0 would normally expand into stores of V0 and V1,
# but both are clobbered by the regmask. Only V0 is re-defined before the
diff --git a/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir b/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
index 0232bd4d82b63..380a8f7331b5e 100644
--- a/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
+++ b/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=hexagon -run-pass prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=hexagon -run-pass prolog-epilog %s -o - | FileCheck %s
# Check that the spill of $q0 no longer uses unaligned store instruction.
# CHECK: V6_vS32b_ai $r16, -256, killed $v0
diff --git a/llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir b/llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
index 465ddd012b134..99da925b950b3 100644
--- a/llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
+++ b/llvm/test/CodeGen/LoongArch/stack-probing-frame-setup.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=loongarch64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
-# RUN: llc -mtriple=loongarch32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+# RUN: llc -mtriple=loongarch64 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+# RUN: llc -mtriple=loongarch32 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
--- |
; Function Attrs: uwtable
diff --git a/llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll b/llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
index ee55ed337a28c..7b7fe1b8dc8d6 100644
--- a/llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
+++ b/llvm/test/CodeGen/LoongArch/statepoint-call-lowering-r1.ll
@@ -1,4 +1,4 @@
-; RUN: llc --mtriple=loongarch64 --verify-machineinstrs --stop-after=prologepilog < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs --stop-after=prolog-epilog < %s | FileCheck %s
;; Check that STATEPOINT instruction has an early clobber implicit def for R1.
diff --git a/llvm/test/CodeGen/M68k/CollapseMOVEM.mir b/llvm/test/CodeGen/M68k/CollapseMOVEM.mir
index e879e1ecccc38..b0d7c5e46bed4 100644
--- a/llvm/test/CodeGen/M68k/CollapseMOVEM.mir
+++ b/llvm/test/CodeGen/M68k/CollapseMOVEM.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=asm -o - \
+# RUN: llc %s -mtriple=m68k -start-after=prolog-epilog -O0 -filetype=asm -o - \
# RUN: | FileCheck %s
#------------------------------------------------------------------------------
diff --git a/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir b/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
index 3e2adff67744a..6891f333454a7 100644
--- a/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
+++ b/llvm/test/CodeGen/M68k/is-pcrel-register-operand-legal.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -mtriple=m68k -start-after=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=m68k -start-after=prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
name: is-pcrel-register-operand-legal
body: |
diff --git a/llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir b/llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir
index bf3d8ec478d18..feeb2fcc766e2 100644
--- a/llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/hasstackframe.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=prologepilog -mtriple arm64-apple-ios -o - -simplify-mir \
+# RUN: llc -run-pass=prolog-epilog -mtriple arm64-apple-ios -o - -simplify-mir \
# RUN: -verify-machineinstrs %s | FileCheck %s
# CHECK: hasStackFrame: true
diff --git a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
index 302f70fc15192..b2bce451dff91 100644
--- a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64 -run-pass=prologepilog -run-pass=aarch64-ptrauth -o - %s 2>&1 | FileCheck --strict-whitespace %s
+# RUN: llc -mtriple=aarch64 -run-pass=prolog-epilog -run-pass=aarch64-ptrauth -o - %s 2>&1 | FileCheck --strict-whitespace %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index d06c8413fd6cc..c76df38d34ab7 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prolog-epilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
index b427c5bdd7229..0872ddb3745a8 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa --start-before=si-lower-sgpr-spills --stop-after=prolog-epilog -o - %s | FileCheck %s
# CHECK: csr_sgpr_spill
# CHECK-NOT: spillPhysVGPRs
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
index 9831f786b847d..3d9a53a78118c 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
@@ -3,7 +3,7 @@
# contains not dead objects only. So using objects IDs as offset in the storage
# caused out of bounds access.
-# RUN: llc -mtriple=amdgcn -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -start-before=si-lower-sgpr-spills -stop-after=prolog-epilog -verify-machineinstrs -o - %s | FileCheck %s
# CHECK-LABEL: name: foo
# CHECK: {{^}}fixedStack: []
diff --git a/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir b/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
index 8811aa84dea6b..b460421f1e259 100644
--- a/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
+++ b/llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
--- |
- ; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s
+ ; RUN: llc --run-pass=prolog-epilog -o - %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7-none-none-eabi"
diff --git a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
index 4fc981b8b77a5..4e9bb4519504c 100644
--- a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
+++ b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
@@ -1,4 +1,4 @@
-# RUN: llc -start-after=prologepilog -filetype=obj -O0 %s -o - -experimental-debug-variable-locations=true | llvm-readobj --codeview - | FileCheck %s
+# RUN: llc -start-after=prolog-epilog -filetype=obj -O0 %s -o - -experimental-debug-variable-locations=true | llvm-readobj --codeview - | FileCheck %s
# Offsets are now CFA, or VFRAME, relative. Both the NRVO sret pointer and the
# string* parameter are on the stack, NRVO at offset 4 (after RA), and Str at
diff --git a/llvm/test/CodeGen/Mips/copy-fp64.ll b/llvm/test/CodeGen/Mips/copy-fp64.ll
index 0f690b0da1821..9a136799bb47c 100644
--- a/llvm/test/CodeGen/Mips/copy-fp64.ll
+++ b/llvm/test/CodeGen/Mips/copy-fp64.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=mips -mcpu=mips32r2 -O0 -relocation-model=pic -mattr=+fp64 \
-; RUN: -stop-before=prologepilog %s -o - | FileCheck %s
+; RUN: -stop-before=prolog-epilog %s -o - | FileCheck %s
declare double @bar(double)
diff --git a/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir b/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
index 4184ad6f7d34a..d56524a604396 100644
--- a/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
+++ b/llvm/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir
@@ -1,5 +1,5 @@
# RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu -enable-shrink-wrap=true \
-# RUN: -start-before=shrink-wrap -stop-after=prologepilog | FileCheck %s
+# RUN: -start-before=shrink-wrap -stop-after=prolog-epilog | FileCheck %s
--- |
declare void @foo()
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
index b99ef4904d549..000492841d307 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \
-; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: -mattr=+altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR32 %s
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
@@ -7,7 +7,7 @@
; RUN: FileCheck --check-prefix=ASM32 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
-; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR64 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
index 9dc06dca3d3b4..63f383b984ef4 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs -mcpu=pwr7 \
-; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: -mattr=+altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR32 %s
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
@@ -7,7 +7,7 @@
; RUN: FileCheck --check-prefix=ASM32 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
-; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR64 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
diff --git a/llvm/test/CodeGen/PowerPC/aix-csr.ll b/llvm/test/CodeGen/PowerPC/aix-csr.ll
index 1dadacf1faab7..131b0273debe3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-csr.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr.ll
@@ -1,12 +1,12 @@
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
-; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR64 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck --check-prefix=ASM64 %s
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
-; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefix=MIR32 %s
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
index 73736d6d5353f..1a912692bf131 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
+# RUN: -run-pass=prolog-epilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK
---
diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
index 16cfa605e809b..1ebcef002d6c5 100644
--- a/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prolog-epilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK %s
-; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
; CHECK-LABEL: name: foo
diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
index 34db2e36dac66..325927846ec23 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prolog-epilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK %s
-; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prolog-epilog -verify-machineinstrs < %s | \
; RUN: FileCheck --check-prefix=CHECK-VEXT %s
; CHECK-LABEL: name: foo
diff --git a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
index bd88b5d89202d..5b1f5ab74d5f9 100644
--- a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
+++ b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
@@ -1,17 +1,17 @@
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu --verify-machineinstrs \
-; RUN: -stop-after=prologepilog < %s | FileCheck \
+; RUN: -stop-after=prolog-epilog < %s | FileCheck \
; RUN: --check-prefixes=CHECK,CHECK64,ELFV2 %s
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 \
-; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK64,V1ANDAIX %s
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 --verify-machineinstrs \
-; RUN: -stop-after=prologepilog < %s | FileCheck \
+; RUN: -stop-after=prolog-epilog < %s | FileCheck \
; RUN: --check-prefixes=CHECK,CHECK64,V1ANDAIX %s
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 \
-; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prolog-epilog < %s | \
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
define dso_local signext i32 @test(i32 signext %n) {
diff --git a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
index 3ce0b22cf174c..4dbb5a864c4a3 100644
--- a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
+++ b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -print-after=prologepilog >%t 2>&1 && FileCheck <%t %s
+; RUN: llc -verify-machineinstrs < %s -print-after=prolog-epilog >%t 2>&1 && FileCheck <%t %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/PowerPC/frame_index_scavenging.mir b/llvm/test/CodeGen/PowerPC/frame_index_scavenging.mir
index 1c96e11eda925..816868adeaeb0 100644
--- a/llvm/test/CodeGen/PowerPC/frame_index_scavenging.mir
+++ b/llvm/test/CodeGen/PowerPC/frame_index_scavenging.mir
@@ -1,16 +1,16 @@
# REQUIRES: asserts
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
-# RUN: -start-before=prologepilog -debug-only=reginfo --filetype=null \
+# RUN: -start-before=prolog-epilog -debug-only=reginfo --filetype=null \
# RUN: -verify-machineinstrs %s 2>&1 >/dev/null | FileCheck %s --check-prefix=P8
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
-# RUN: -start-before=prologepilog -debug-only=reginfo --filetype=null \
+# RUN: -start-before=prolog-epilog -debug-only=reginfo --filetype=null \
# RUN: -verify-machineinstrs %s 2>&1 >/dev/null | FileCheck %s --check-prefix=P9
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
-# RUN: -start-before=prologepilog -debug-only=reginfo \
+# RUN: -start-before=prolog-epilog -debug-only=reginfo \
# RUN: --filetype=null -ppc-enable-pe-vector-spills \
# RUN: -verify-machineinstrs %s 2>&1 >/dev/null | FileCheck %s --check-prefix=P9-REGSPILL
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 \
-# RUN: -start-before=prologepilog -debug-only=reginfo --filetype=null \
+# RUN: -start-before=prolog-epilog -debug-only=reginfo --filetype=null \
# RUN: -verify-machineinstrs %s 2>&1 >/dev/null | FileCheck %s -check-prefix=P10
---
diff --git a/llvm/test/CodeGen/PowerPC/mflr-store.mir b/llvm/test/CodeGen/PowerPC/mflr-store.mir
index 34874151f5fb9..460b13ef9fb20 100644
--- a/llvm/test/CodeGen/PowerPC/mflr-store.mir
+++ b/llvm/test/CodeGen/PowerPC/mflr-store.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir \
-# RUN: -stop-after=prologepilog --verify-machineinstrs < %s | \
+# RUN: -stop-after=prolog-epilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK
---
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
index 196ad134bfa55..0392da8d637e6 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -1,14 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: -run-pass=prolog-epilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefix=SAVEONE
# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: -run-pass=prolog-epilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefix=SAVEALL
# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \
-# RUN: -run-pass=prologepilog --verify-machineinstrs %s -o - | \
+# RUN: -run-pass=prolog-epilog --verify-machineinstrs %s -o - | \
# RUN: FileCheck %s --check-prefix=SAVEALL
---
diff --git a/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir b/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
index 59ab2fce083c7..2ef91c073ee94 100644
--- a/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
+++ b/llvm/test/CodeGen/PowerPC/prolog_vec_spills.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prologepilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
+# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=prolog-epilog -ppc-enable-pe-vector-spills %s -o - | FileCheck %s
---
name: test1BB
diff --git a/llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir b/llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
index b0615959d91c6..bee4cdad217de 100644
--- a/llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
+++ b/llvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
@@ -1,5 +1,5 @@
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
-# RUN: -start-before=prologepilog -ppc-enable-pe-vector-spills \
+# RUN: -start-before=prolog-epilog -ppc-enable-pe-vector-spills \
# RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir b/llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
index b7b4babddb3d4..ab360334ea6d3 100644
--- a/llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
+++ b/llvm/test/CodeGen/RISCV/determine-callee-saves-gpr.mir
@@ -1,13 +1,13 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -o - %s \
+# RUN: llc -mtriple=riscv64 -run-pass=prolog-epilog -o - %s \
# RUN: | FileCheck %s -check-prefixes=RV64I
-# RUN: llc -mtriple=riscv64 -mattr=+zcmp -run-pass=prologepilog -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+zcmp -run-pass=prolog-epilog -o - %s \
# RUN: | FileCheck %s -check-prefixes=RV64I-ZCMP
-# RUN: llc -mtriple=riscv64 -frame-pointer=all -run-pass=prologepilog -o - %s \
+# RUN: llc -mtriple=riscv64 -frame-pointer=all -run-pass=prolog-epilog -o - %s \
# RUN: | FileCheck %s -check-prefixes=RV64I-FP
-# RUN: llc -mtriple=riscv64 -mattr=+zcmp -frame-pointer=all -run-pass=prologepilog -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+zcmp -frame-pointer=all -run-pass=prolog-epilog -o - %s \
# RUN: | FileCheck %s -check-prefixes=RV64I-ZCMP-FP
-# RUN: llc -mtriple=riscv64 -mattr=+save-restore -run-pass=prologepilog -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+save-restore -run-pass=prolog-epilog -o - %s \
# RUN: | FileCheck %s -check-prefixes=RV64I-SR
--- |
diff --git a/llvm/test/CodeGen/RISCV/live-sp.mir b/llvm/test/CodeGen/RISCV/live-sp.mir
index b8d69625e6a95..ac335788e3f8f 100644
--- a/llvm/test/CodeGen/RISCV/live-sp.mir
+++ b/llvm/test/CodeGen/RISCV/live-sp.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -simplify-mir -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=prolog-epilog -simplify-mir -o - %s | FileCheck %s
# verify live-on-entry registers are not marked killed by spills
--- |
diff --git a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
index 5f6f3bf818d63..fffab82fe5ca9 100644
--- a/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# REQUIRES: asserts
-# RUN: llc -mtriple riscv64 -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
#
-# RUN: llc -mtriple riscv64 -start-before=prologepilog -o /dev/null \
-# RUN: -debug-only=prologepilog -verify-machineinstrs %s 2>&1 \
+# RUN: llc -mtriple riscv64 -start-before=prolog-epilog -o /dev/null \
+# RUN: -debug-only=prolog-epilog -verify-machineinstrs %s 2>&1 \
# RUN: | FileCheck --check-prefix=DEBUG %s
#
# DEBUG: Adjusting emergency spill slots!
diff --git a/llvm/test/CodeGen/RISCV/pr53662.mir b/llvm/test/CodeGen/RISCV/pr53662.mir
index dccad40368111..be4f1f47dc36c 100644
--- a/llvm/test/CodeGen/RISCV/pr53662.mir
+++ b/llvm/test/CodeGen/RISCV/pr53662.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=prolog-epilog -o - %s | FileCheck %s
--- |
define void @b() {
entry:
diff --git a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
index 5619099468303..dabf65824cc0a 100644
--- a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv32.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
---
name: main
diff --git a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir
index 7d8cf0889f664..25552560a894c 100644
--- a/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/riscv-scavenge-crash-2nd-pass-rv64.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv64 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
---
name: test
diff --git a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
index 83ee899894ae4..3d7cbd098e1ee 100644
--- a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prolog-epilog < %s | FileCheck %s
; Check that STATEPOINT instruction has an early clobber implicit def for LR.
target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
index cb2bf2ceec2ed..618dfbec14c71 100644
--- a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prolog-epilog < %s | FileCheck %s
; Check that STATEPOINT instruction prefer to use x2 in presense of x8.
target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
index 64430c916cddb..296457857e2b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass prolog-epilog %s -o - | FileCheck %s
--- |
declare void @extern(ptr) #0
diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
index c733ddf591c4b..b0f39365eea72 100644
--- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=prolog-epilog %s -o - 2>&1 | FileCheck %s
--- |
define void @add_scalable_offset(
diff --git a/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir b/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
index 1e8aea92c9780..394b9c4f0abb4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
@@ -1,7 +1,7 @@
# RUN: llc -mtriple=riscv64 -mattr=+v -o %t0 -filetype=obj \
-# RUN: -start-before=prologepilog %s
+# RUN: -start-before=prolog-epilog %s
# RUN: llc -mtriple=riscv64 -mattr=+v -o %t1 -filetype=obj \
-# RUN: -frame-pointer=all -start-before=prologepilog %s
+# RUN: -frame-pointer=all -start-before=prolog-epilog %s
# RUN: llvm-dwarfdump --name="value0" %t0 | FileCheck %s --check-prefix=CHECK0-PLUS
# RUN: llvm-dwarfdump --name="value1" %t0 | FileCheck %s --check-prefix=CHECK1-PLUS
# RUN: llvm-dwarfdump --name="value2" %t0 | FileCheck %s --check-prefix=CHECK2-PLUS
diff --git a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
index d8cc861ccff8e..12f5694516deb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
index 071e3a8cf1227..3de992f30c2b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
index 1d9b8b2d429be..1731ab3e372e3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -o - %s \
-# RUN: -stop-after=prologepilog | FileCheck %s
+# RUN: -stop-after=prolog-epilog | FileCheck %s
--- |
define void @foo() !dbg !0 {
diff --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
index 9d02dc79dde2f..4b12a64d7cf31 100644
--- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv64 -mattr=+m,+v -target-abi=lp64 -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+m,+v -target-abi=lp64 -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
index 8ebf7fa85ec88..0179525e7c896 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-# RUN: -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
+# RUN: -start-after finalize-isel -stop-after prolog-epilog -o - %s | FileCheck %s
--- |
define void @mask_reg_alloc() {
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
index c0170e7db5f2a..6fbf9abe5bfa7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
-# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prolog-epilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir
index 7457971809fd2..87617908c60a4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prolog-epilog -o - %s | FileCheck %s --check-prefix=MIR
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM
---
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
index 7c9574e4a806f..646e0ff7c16e9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prologepilog \
+# RUN: llc -mtriple riscv64 -mattr=+m,+v -run-pass=prolog-epilog \
# RUN: -riscv-v-vector-bits-min=512 -o - %s | FileCheck %s
#
# Stack layout of this program
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
index e3f2a4313630d..3fc0c1666a698 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -o - %s \
-# RUN: -start-before=prologepilog | FileCheck %s
+# RUN: -start-before=prolog-epilog | FileCheck %s
#
# These tests check that we are assigning the right stack slot to GPRs and to
# vector registers (VRs). If this test changes, make sure there is no overlap
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
index a78691557b643..19c3d727e349f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+m,+v -o - %s \
-# RUN: -start-before=prologepilog | FileCheck %s
+# RUN: -start-before=prolog-epilog | FileCheck %s
#
# This test checks that we are assigning the right stack slot to GPRs and to
# vector registers (VRs). If this test changes, make sure there is no overlap
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
index cc9cdb45ad6ff..a67dd2289f928 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv64 -mattr=+v -start-before=greedy -stop-after=prologepilog %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -start-before=greedy -stop-after=prolog-epilog %s -o - 2>&1 | FileCheck %s
--- |
define void @zvlsseg_spill_0(ptr %base, i64 %vl) {
diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll b/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
index e4a15ce457047..1a0008d625cf5 100644
--- a/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
+++ b/llvm/test/CodeGen/RISCV/shadowcallstack-frame-flags.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-zicfiss \
-; RUN: -verify-machineinstrs -stop-after=prologepilog \
+; RUN: -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s --check-prefix=RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zicfiss \
-; RUN: -verify-machineinstrs -stop-after=prologepilog \
+; RUN: -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s --check-prefix=RV64
declare i32 @bar()
diff --git a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
index bd31662ae2dac..ae96be12e3f64 100644
--- a/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
+++ b/llvm/test/CodeGen/RISCV/stack-inst-compress.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK-RV32-NO-COM %s
-# RUN: llc -mtriple=riscv32 -mattr=+c -x mir -run-pass=prologepilog \
+# RUN: llc -mtriple=riscv32 -mattr=+c -x mir -run-pass=prolog-epilog \
# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV32-COM %s
-# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=CHECK-RV64-NO-COM %s
-# RUN: llc -mtriple=riscv64 -mattr=+c -x mir -run-pass=prologepilog \
+# RUN: llc -mtriple=riscv64 -mattr=+c -x mir -run-pass=prolog-epilog \
# RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-RV64-COM %s
--- |
define dso_local void @_Z15stack_size_2048v() {
diff --git a/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir b/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
index ad7273a29238f..b5c4b68d68fbc 100644
--- a/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
+++ b/llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s \
# RUN: | FileCheck %s -check-prefixes=RV64I
-# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=prolog-epilog -verify-machineinstrs < %s \
# RUN: | FileCheck %s -check-prefixes=RV32I
--- |
; Function Attrs: uwtable
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir b/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir
index 4f797433ce4aa..71c26f6ba87a6 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir
+++ b/llvm/test/CodeGen/RISCV/xqccmp-cm-popretz.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP32 %s
-# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP64 %s
---
name: popret_rvlist5
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir b/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir
index 7ed481ae5a49e..63d0e189da3e4 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir
+++ b/llvm/test/CodeGen/RISCV/xqccmp-cm-push-pop.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+xqccmp -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP32 %s
-# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+xqccmp -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-XQCCMP64 %s
---
name: push_rvlist15
diff --git a/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
index 1cdb35256723e..3207a218c7422 100644
--- a/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
+++ b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
@@ -1,15 +1,15 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s
-# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s
-# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s
-# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s
-# RUN: llc -mtriple=riscv32 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s
-# RUN: llc -mtriple=riscv64 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -x mir -start-before=prolog-epilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s
---
name: popret_rvlist5
diff --git a/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir b/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
index 9cc84216e61fc..0ca9595e6af36 100644
--- a/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
+++ b/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
@@ -1,15 +1,15 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s
-# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s
-# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s
-# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s
-# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv32 -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s
-# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=prolog-epilog -verify-machineinstrs -o - %s \
# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s
---
name: push_rvlist15
diff --git a/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir b/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
index 979b8a4e17d5a..b658b66dc28e2 100644
--- a/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
+++ b/llvm/test/CodeGen/RISCV/zcmp-prolog-epilog-crash.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# REQUIRES: asserts
-# RUN: llc %s -o - -mtriple=riscv32 -mattr=+zcmp -target-abi ilp32 -run-pass=prologepilog \
+# RUN: llc %s -o - -mtriple=riscv32 -mattr=+zcmp -target-abi ilp32 -run-pass=prolog-epilog \
# RUN: -simplify-mir -verify-machineinstrs | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir b/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
index f8b2b542a497d..1889ad8924a61 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
+++ b/llvm/test/CodeGen/RISCV/zdinx-large-spill.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-# RUN: llc %s -mtriple=riscv32 -mattr=+zdinx -start-before=prologepilog -o - | FileCheck %s
+# RUN: llc %s -mtriple=riscv32 -mattr=+zdinx -start-before=prolog-epilog -o - | FileCheck %s
# We want to make sure eliminateFrameIndex doesn't fold sp+2044 as an offset in
# a GPR pair spill/reload instruction. When we split the pair spill, we would be
diff --git a/llvm/test/CodeGen/RISCV/zdinx-spill.ll b/llvm/test/CodeGen/RISCV/zdinx-spill.ll
index 79a242a494f78..6a57805696690 100644
--- a/llvm/test/CodeGen/RISCV/zdinx-spill.ll
+++ b/llvm/test/CodeGen/RISCV/zdinx-spill.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -stop-after=prologepilog | FileCheck %s -check-prefix=ZDINX
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs -stop-after=prologepilog | FileCheck %s -check-prefix=ZDINX-ZILSD
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd,+unaligned-scalar-mem -verify-machineinstrs -stop-after=prologepilog | FileCheck %s -check-prefix=ZDINX-ZILSD-UNALIGNED
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd,+zilsd-word-align -verify-machineinstrs -stop-after=prologepilog | FileCheck %s -check-prefix=ZDINX-ZILSD-4BYTEALIGN
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -stop-after=prolog-epilog | FileCheck %s -check-prefix=ZDINX
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd -verify-machineinstrs -stop-after=prolog-epilog | FileCheck %s -check-prefix=ZDINX-ZILSD
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd,+unaligned-scalar-mem -verify-machineinstrs -stop-after=prolog-epilog | FileCheck %s -check-prefix=ZDINX-ZILSD-UNALIGNED
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zdinx,+zilsd,+zilsd-word-align -verify-machineinstrs -stop-after=prolog-epilog | FileCheck %s -check-prefix=ZDINX-ZILSD-4BYTEALIGN
declare void @bar()
diff --git a/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir b/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir
index 5fda434cab827..315d0681224bc 100644
--- a/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir
+++ b/llvm/test/CodeGen/RISCV/zilsd-csr-duplicate.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple riscv32 -mattr=+zcmp,+zilsd --run-pass=prologepilog %s -verify-machineinstrs -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zcmp,+zilsd --run-pass=prolog-epilog %s -verify-machineinstrs -o - \
# RUN: | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/zilsd-spill.ll b/llvm/test/CodeGen/RISCV/zilsd-spill.ll
index d9254848fe041..67a20ac5f7c4c 100644
--- a/llvm/test/CodeGen/RISCV/zilsd-spill.ll
+++ b/llvm/test/CodeGen/RISCV/zilsd-spill.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs -stop-after=prologepilog \
+; RUN: llc < %s -mtriple=riscv32 -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd -verify-machineinstrs -stop-after=prologepilog \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s -check-prefix=RV32I-ZILSD
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd,+unaligned-scalar-mem -verify-machineinstrs -stop-after=prologepilog \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd,+unaligned-scalar-mem -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s -check-prefix=RV32I-ZILSD-UNALIGNED
-; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd,+zilsd-word-align -verify-machineinstrs -stop-after=prologepilog \
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zilsd,+zilsd-word-align -verify-machineinstrs -stop-after=prolog-epilog \
; RUN: | FileCheck %s -check-prefix=RV32I-ZILSD-4BYTEALIGN
define i64 @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind {
diff --git a/llvm/test/CodeGen/SystemZ/frame-26.mir b/llvm/test/CodeGen/SystemZ/frame-26.mir
index becd176cfb1b8..ded761b0cce70 100644
--- a/llvm/test/CodeGen/SystemZ/frame-26.mir
+++ b/llvm/test/CodeGen/SystemZ/frame-26.mir
@@ -1,10 +1,10 @@
-# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -print-after=prologepilog \
+# RUN: llc -mtriple=s390x-linux-gnu -start-before=prolog-epilog %s -o - -print-after=prolog-epilog \
# RUN: -verify-machineinstrs 2>&1 | FileCheck %s
#
# Test that R6 when used for an argument is modelled as being live throughout
# the function when not saved in the prologue..
-# CHECK: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
+# CHECK: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prolog-epilog) ***:
# CHECK-NEXT: # Machine code for function fun0:
# CHECK-LABEL: bb.0:
# CHECK: liveins:{{.*}} $r6d
diff --git a/llvm/test/CodeGen/SystemZ/frame-27.mir b/llvm/test/CodeGen/SystemZ/frame-27.mir
index 4cb0206e7210c..faadd0e8ba8b9 100644
--- a/llvm/test/CodeGen/SystemZ/frame-27.mir
+++ b/llvm/test/CodeGen/SystemZ/frame-27.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -mcpu=z14 \
-# RUN: -debug-only=prologepilog -print-after=prologepilog -verify-machineinstrs 2>&1 \
+# RUN: llc -mtriple=s390x-linux-gnu -start-before=prolog-epilog %s -o - -mcpu=z14 \
+# RUN: -debug-only=prolog-epilog -print-after=prolog-epilog -verify-machineinstrs 2>&1 \
# RUN: | FileCheck %s
# REQUIRES: asserts
#
diff --git a/llvm/test/CodeGen/SystemZ/frame-28.mir b/llvm/test/CodeGen/SystemZ/frame-28.mir
index 353fe3dec9a3b..4173baf3f4950 100644
--- a/llvm/test/CodeGen/SystemZ/frame-28.mir
+++ b/llvm/test/CodeGen/SystemZ/frame-28.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -mcpu=z14 \
+# RUN: llc -mtriple=s390x-linux-gnu -start-before=prolog-epilog %s -o - -mcpu=z14 \
# RUN: -verify-machineinstrs 2>&1 | FileCheck %s
#
# Test that redundant frame addressing anchor points are removed by
diff --git a/llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir b/llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir
index ecd7dd371cb04..ffd609ba32172 100644
--- a/llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir
+++ b/llvm/test/CodeGen/SystemZ/scavenge-clobbered-reg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc %s -mtriple=s390x-ibm-linux -mcpu=z15 -run-pass=prologepilog -o - | FileCheck %s
+# RUN: llc %s -mtriple=s390x-ibm-linux -mcpu=z15 -run-pass=prolog-epilog -o - | FileCheck %s
---
name: repro
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/SystemZ/tls-11.mir b/llvm/test/CodeGen/SystemZ/tls-11.mir
index 623a8ab519f73..180ab4686cd62 100644
--- a/llvm/test/CodeGen/SystemZ/tls-11.mir
+++ b/llvm/test/CodeGen/SystemZ/tls-11.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z196 -O0 -start-before=prologepilog \
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z196 -O0 -start-before=prolog-epilog \
# RUN: -o - %s | FileCheck %s
#
# Test that a COPY to CC gets implemented with a tmlh or tmhh depending on
diff --git a/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir b/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
index f55f2b2e919dc..a9f3c642d28af 100644
--- a/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
+++ b/llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 -run-pass=stack-protector -run-pass=prolog-epilog | FileCheck %s
---
name: func0
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir b/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
index acab7e7002611..060269e203eb1 100644
--- a/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
+++ b/llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -run-pass=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -run-pass=prolog-epilog | FileCheck %s
--- |
; Function Attrs: noinline nounwind optnone
define dso_local i64 @f() #0 {
diff --git a/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir b/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
index fecd8e799657d..5ae6a7c4a3980 100644
--- a/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
+++ b/llvm/test/CodeGen/Thumb2/mve-stacksplot.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prolog-epilog | FileCheck %s
---
name: func0
tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir
index bfe55a5bc3cb4..fd2396438557e 100644
--- a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir
+++ b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=thumbv7-unknown-linux-android30 -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=thumbv7-unknown-linux-android30 -run-pass=prolog-epilog -verify-machineinstrs %s -o - | FileCheck %s
# When saving and restoring callee-saved registers, LR is saved but not restored,
# because it is reloaded directly into PC. Therefore it should be available to scavenge
diff --git a/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir b/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
index 43b394721b5c9..59d6175a9a48a 100644
--- a/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
+++ b/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prologepilog 2>&1 | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prolog-epilog 2>&1 | FileCheck %s
--- |
define i64 @_Z3foob(i1 zeroext %cond) #0 {
ret i64 0
diff --git a/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir b/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
index 243d800200c29..11cda26bca970 100644
--- a/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
+++ b/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prologepilog 2>&1 | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prolog-epilog 2>&1 | FileCheck %s
--- |
declare dso_local void @_Z3goov()
define i64 @_Z3foob(i1 zeroext %cond) #0 {
diff --git a/llvm/test/CodeGen/X86/cfi-xmm.ll b/llvm/test/CodeGen/X86/cfi-xmm.ll
index dde731c5cbdfb..68c001bb9c86f 100644
--- a/llvm/test/CodeGen/X86/cfi-xmm.ll
+++ b/llvm/test/CodeGen/X86/cfi-xmm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-; RUN: llc < %s -mtriple x86_64-w64-windows-gnu -exception-model=dwarf -stop-after=prologepilog | FileCheck %s --check-prefix=PEI
+; RUN: llc < %s -mtriple x86_64-w64-windows-gnu -exception-model=dwarf -stop-after=prolog-epilog | FileCheck %s --check-prefix=PEI
define void @_Z1fv() {
; PEI-LABEL: name: _Z1fv
diff --git a/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll b/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
index 24a1da68f7dea..aa2694f05e2e3 100644
--- a/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
+++ b/llvm/test/CodeGen/X86/epilogue-cfi-fp.ll
@@ -1,5 +1,5 @@
; RUN: llc -O0 %s -o - | FileCheck %s
-; RUN: llc < %s -stop-after=prologepilog | FileCheck %s --check-prefix=PEI
+; RUN: llc < %s -stop-after=prolog-epilog | FileCheck %s --check-prefix=PEI
target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
target triple = "i686-pc-linux"
diff --git a/llvm/test/CodeGen/X86/ipra-inline-asm.ll b/llvm/test/CodeGen/X86/ipra-inline-asm.ll
index 09b8bdd790091..ea4b76eda4e76 100644
--- a/llvm/test/CodeGen/X86/ipra-inline-asm.ll
+++ b/llvm/test/CodeGen/X86/ipra-inline-asm.ll
@@ -1,6 +1,6 @@
; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
-; RUN: llc --stop-after=prologepilog -o - %s \
+; RUN: llc --stop-after=prolog-epilog -o - %s \
; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll
index f270f8fc741aa..c008d691ee841 100644
--- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll
+++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll
@@ -1,6 +1,6 @@
; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
-; RUN: llc -stop-after=prologepilog -o - %s \
+; RUN: llc -stop-after=prolog-epilog -o - %s \
; RUN: | llc -x=mir -enable-ipra -passes="module(require<reg-usage>,function(machine-function(reg-usage-collector)),print<reg-usage>)" -o /dev/null 2>&1 \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/X86/prologepilog_deref_size.mir b/llvm/test/CodeGen/X86/prologepilog_deref_size.mir
index 7764eb14f0d8a..73699f93ae425 100644
--- a/llvm/test/CodeGen/X86/prologepilog_deref_size.mir
+++ b/llvm/test/CodeGen/X86/prologepilog_deref_size.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog -o - %s | FileCheck %s
--- |
; ModuleID = 'dbg.opt.ll'
source_filename = "dbg.c"
diff --git a/llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir b/llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir
index 39d06c2909f9e..89b50d7b78692 100644
--- a/llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir
+++ b/llvm/test/CodeGen/X86/prologue-epilogue-remarks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-unknown-unknown -run-pass=prologepilog -pass-remarks-output=%t -pass-remarks-analysis=prologepilog -o /dev/null %s 2>&1
+# RUN: llc -mtriple=x86_64-unknown-unknown -run-pass=prolog-epilog -pass-remarks-output=%t -pass-remarks-analysis=prolog-epilog -o /dev/null %s 2>&1
# RUN: cat %t | FileCheck %s
--- |
@@ -12,7 +12,7 @@ name: fun0
stack:
- { id: 0, type: default, offset: 0, size: 8, alignment: 4 }
# --- !Analysis
-# CHECK: Pass: prologepilog
+# CHECK: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK-NEXT: Function: fun0
# CHECK-NEXT: Args:
@@ -33,7 +33,7 @@ name: fun1
stack:
- { id: 0, type: default, offset: 0, size: 19, alignment: 4 }
# --- !Analysis
-# CHECK: Pass: prologepilog
+# CHECK: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK-NEXT: Function: fun1
# CHECK-NEXT: Args:
@@ -53,7 +53,7 @@ name: fun2
stack:
- { id: 0, type: default, offset: 0, size: 1024, alignment: 8 }
# --- !Analysis
-# CHECK: Pass: prologepilog
+# CHECK: Pass: prolog-epilog
# CHECK-NEXT: Name: StackSize
# CHECK-NEXT: Function: fun2
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/X86/push-cfi.ll b/llvm/test/CodeGen/X86/push-cfi.ll
index 7bbd5142e7391..b273eaa2b1b2a 100644
--- a/llvm/test/CodeGen/X86/push-cfi.ll
+++ b/llvm/test/CodeGen/X86/push-cfi.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s -check-prefix=LINUX -check-prefix=CHECK
; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=DARWIN -check-prefix=CHECK
-; RUN: llc < %s -mtriple=i686-pc-linux -stop-after=prologepilog | FileCheck %s --check-prefix=PEI
+; RUN: llc < %s -mtriple=i686-pc-linux -stop-after=prolog-epilog | FileCheck %s --check-prefix=PEI
declare i32 @__gxx_personality_v0(...)
declare void @good(i32 %a, i32 %b, i32 %c, i32 %d)
diff --git a/llvm/test/CodeGen/X86/throws-cfi-fp.ll b/llvm/test/CodeGen/X86/throws-cfi-fp.ll
index 1ad12823ec67e..c6fc8bda52010 100644
--- a/llvm/test/CodeGen/X86/throws-cfi-fp.ll
+++ b/llvm/test/CodeGen/X86/throws-cfi-fp.ll
@@ -1,5 +1,5 @@
; RUN: llc %s -o - | FileCheck %s
-; RUN: llc < %s -stop-after=prologepilog | FileCheck %s --check-prefix=PEI
+; RUN: llc < %s -stop-after=prolog-epilog | FileCheck %s --check-prefix=PEI
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll b/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
index 549c9642ff134..735a37079bc68 100644
--- a/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
+++ b/llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
-; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
+; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after prolog-epilog %s | FileCheck %s --check-prefix=POST-RA
; This test verifies that the virtual register references in machine function's
; liveins are cleared after register allocation.
diff --git a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
index d95bfc0810d3e..46d55da5d88c5 100644
--- a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
+++ b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir
@@ -1,4 +1,4 @@
-# RUN: llc -verify-machineinstrs %s -run-pass prologepilog -mtriple=x86_64-pc-win32-coreclr -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs %s -run-pass prolog-epilog -mtriple=x86_64-pc-win32-coreclr -o - | FileCheck %s
...
---
name: main4k
diff --git a/llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir b/llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
index be022e37dfc7f..aad13fb396970 100644
--- a/llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
+++ b/llvm/test/CodeGen/X86/zero-call-used-regs-debug-info.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass=prologepilog -o - %s | FileCheck %s
+# RUN: llc -run-pass=prolog-epilog -o - %s | FileCheck %s
# Test that the presence of debug instructions doesn't trigger arbitrary registers that are unused to be zeroed out.
diff --git a/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir b/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir
index 3e8a9db2cb047..3f661cf20d1b8 100644
--- a/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir
+++ b/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir
@@ -1,4 +1,4 @@
-# RUN: llc -verify-machineinstrs -start-after=prologepilog -filetype=obj -o - %s | llvm-dwarfdump -v --debug-info - | FileCheck %s
+# RUN: llc -verify-machineinstrs -start-after=prolog-epilog -filetype=obj -o - %s | llvm-dwarfdump -v --debug-info - | FileCheck %s
# CHECK: .debug_info contents:
# CHECK: DW_TAG_variable
# CHECK-NEXT: DW_AT_location {{.*}} (DW_OP_reg1 RDX, DW_OP_bit_piece 0x8 0x8)
diff --git a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
index 2bafcc2944bbe..5b0e05a153434 100644
--- a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
@@ -1,6 +1,6 @@
# Verify that a CFI instruction with no debug location
# does not result in a line-0 location in the assembler.
-# RUN: %llc_dwarf -start-after=prologepilog -mtriple=x86_64 -use-unknown-locations=Enable %s -o - | FileCheck %s
+# RUN: %llc_dwarf -start-after=prolog-epilog -mtriple=x86_64 -use-unknown-locations=Enable %s -o - | FileCheck %s
#
# CHECK-NOT: .loc 1 0
# CHECK: .cfi_def_cfa_offset
diff --git a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
index 4df967ce03493..2438a57a7d243 100644
--- a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
+++ b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -x mir -o - -mtriple=x86_64-unknown-unknown -run-pass=prologepilog | FileCheck %s
+# RUN: llc %s -x mir -o - -mtriple=x86_64-unknown-unknown -run-pass=prolog-epilog | FileCheck %s
#
# Check when the DBG_VALUE on a stack slot below (for var "c") has its stack
# slot replaced with $rsp and a complex expression, it has DW_OP_stack_value
diff --git a/llvm/test/DebugInfo/X86/prolog-params.mir b/llvm/test/DebugInfo/X86/prolog-params.mir
index 6629dca810f95..31a57475bfb27 100644
--- a/llvm/test/DebugInfo/X86/prolog-params.mir
+++ b/llvm/test/DebugInfo/X86/prolog-params.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass=prolog-epilog %s -o - | FileCheck %s
# MIR test case produced by compiling:
#
diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml
index 9aa711a9068c2..9cb7eeadf71a6 100644
--- a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml
+++ b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic1.macho.remarks.arm64.opt.yaml
@@ -12,7 +12,7 @@ Args:
- String: ' because its definition is unavailable'
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: basic1.c, Line: 37, Column: 0 }
Function: main
diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml
index 4aa53015a988f..888c381bfc7cb 100644
--- a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml
+++ b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic2.macho.remarks.arm64.opt.yaml
@@ -78,7 +78,7 @@ Args:
DebugLoc: { File: basic2.c, Line: 20, Column: 10 }
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: basic2.c, Line: 10, Column: 0 }
Function: unused1
@@ -89,7 +89,7 @@ Args:
- String: ''''
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: basic2.c, Line: 19, Column: 0 }
Function: foo
diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
index 8570049fab6b0..80177f8940515 100644
--- a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
+++ b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/basic3.macho.remarks.arm64.opt.yaml
@@ -52,7 +52,7 @@ Args:
- String: ';'
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: basic3.c, Line: 7, Column: 0 }
Function: unused2
@@ -63,7 +63,7 @@ Args:
- String: ''''
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: basic3.c, Line: 16, Column: 0 }
Function: bar
diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
index e6aa3454d4007..8af69aaeaea43 100644
--- a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
+++ b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64.opt.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: fat.macho.remarks.x86.c, Line: 14, Column: 0 }
Function: main
diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
index e6aa3454d4007..8af69aaeaea43 100644
--- a/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
+++ b/llvm/test/tools/dsymutil/Inputs/private/tmp/remarks/fat.macho.remarks.x86_64h.opt.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
DebugLoc: { File: fat.macho.remarks.x86.c, Line: 14, Column: 0 }
Function: main
diff --git a/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream b/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
index 49ba47e2504ed..3b18cdc129c73 100644
Binary files a/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream and b/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.bitstream
diff er
diff --git a/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml b/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
index ae02fc1102d0b..88abec958704c 100644
--- a/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
+++ b/llvm/test/tools/llvm-remarkutil/Inputs/two-remarks.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/convert.test b/llvm/test/tools/llvm-remarkutil/convert.test
index 2b1bdcb0a5b3a..0023663dbe3b0 100644
--- a/llvm/test/tools/llvm-remarkutil/convert.test
+++ b/llvm/test/tools/llvm-remarkutil/convert.test
@@ -7,7 +7,7 @@ RUN: llvm-remarkutil bitstream2yaml %t.bitstream -o - | FileCheck %s -strict-whi
; ERR: error: Unsupported remark container version (expected: 1, read: 0). Please upgrade/downgrade your toolchain to read this container.
; CHECK: --- !Analysis
-; CHECK-NEXT: Pass: prologepilog
+; CHECK-NEXT: Pass: prolog-epilog
; CHECK-NEXT: Name: StackSize
; CHECK-NEXT: Function: func0
; CHECK-NEXT: Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-1-instr-1-stack.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-1-instr-1-stack.yaml
index ae02fc1102d0b..88abec958704c 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-1-instr-1-stack.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-1-instr-1-stack.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-2-instr-2-stack.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-2-instr-2-stack.yaml
index f44ad697d2e3c..5e23514fbcedc 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-2-instr-2-stack.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/1-func-2-instr-2-stack.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/2-identical-func-1-instr-1-stack.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/2-identical-func-1-instr-1-stack.yaml
index 22e4b1b944ce3..38dda98198228 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/2-identical-func-1-instr-1-stack.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/2-identical-func-1-instr-1-stack.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
@@ -15,7 +15,7 @@ Args:
- String: ' instructions in function'
...
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func1
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/inconvertible-integer.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/inconvertible-integer.yaml
index 106e0b2519dfa..7ab044480381c 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/inconvertible-integer.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/inconvertible-integer.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/no-instruction-count-remarks.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/no-instruction-count-remarks.yaml
index d765cb8de48b0..f41798f72598d 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/no-instruction-count-remarks.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/no-instruction-count-remarks.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/unexpected-key.yaml b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/unexpected-key.yaml
index 450fbcc77681b..d7b831524a70a 100644
--- a/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/unexpected-key.yaml
+++ b/llvm/test/tools/llvm-remarkutil/size-
diff /Inputs/unexpected-key.yaml
@@ -1,5 +1,5 @@
--- !Analysis
-Pass: prologepilog
+Pass: prolog-epilog
Name: StackSize
Function: func0
Args:
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 767e1079de820..25aff57faa879 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -323,7 +323,7 @@ Error assembleToStream(const ExegesisTarget &ET,
// Adding the following passes:
// - postrapseudos: expands pseudo return instructions used on some targets.
// - prologepilog: saves and restore callee saved registers.
- for (const char *PassName : {"postrapseudos", "prologepilog"})
+ for (const char *PassName : {"postrapseudos", "prolog-epilog"})
if (addPass(PM, PassName, *TPC))
return make_error<Failure>("Unable to add a mandatory pass");
TPC->setInitialized();
diff --git a/llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp b/llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
index d3cb134279a26..6167f81b0e5c8 100644
--- a/llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
+++ b/llvm/tools/llvm-remarkutil/RemarkSizeDiff.cpp
@@ -265,7 +265,7 @@ static Error processRemark(const remarks::Remark &Remark,
++NumInstCountRemarksParsed;
}
// Collect remarks which contain the stack size of a function.
- else if (PassName == "prologepilog" && RemarkName == "StackSize") {
+ else if (PassName == "prolog-epilog" && RemarkName == "StackSize") {
// Expecting the 0-th argument to have the key "NumStackBytes" and an
// integer value.
auto MaybeStackSize =
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