[flang-commits] [flang] 36b339b - [flang][cuda] Relax assertion for atomicexch (#128582)

[via flang-commits]

Author: Valentin Clement (バレンタイン クレメン)
Date: 2025-02-24T14:25:35-08:00
New Revision: 36b339b84a98afe7bdf470747a776d0d5f348b64

URL: https://github.com/llvm/llvm-project/commit/36b339b84a98afe7bdf470747a776d0d5f348b64
DIFF: https://github.com/llvm/llvm-project/commit/36b339b84a98afe7bdf470747a776d0d5f348b64.diff

LOG: [flang][cuda] Relax assertion for atomicexch (#128582)

atomicexch interfaces accepts also floating point numbers. Relax the
assertion so float are also accepted.

Added: 
    

Modified: 
    flang/lib/Optimizer/Builder/IntrinsicCall.cpp
    flang/test/Lower/CUDA/cuda-device-proc.cuf

Removed: 
    


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diff  --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
index c4dcd7f3573d1..537c817e32ad8 100644
--- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
+++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp
@@ -2760,7 +2760,7 @@ mlir::Value IntrinsicLibrary::genAtomicDec(mlir::Type resultType,
 mlir::Value IntrinsicLibrary::genAtomicExch(mlir::Type resultType,
                                             llvm::ArrayRef<mlir::Value> args) {
   assert(args.size() == 2);
-  assert(mlir::isa<mlir::IntegerType>(args[1].getType()));
+  assert(args[1].getType().isIntOrFloat());
 
   mlir::LLVM::AtomicBinOp binOp = mlir::LLVM::AtomicBinOp::xchg;
   return genAtomBinOp(builder, loc, binOp, args[0], args[1]);

diff  --git a/flang/test/Lower/CUDA/cuda-device-proc.cuf b/flang/test/Lower/CUDA/cuda-device-proc.cuf
index 6487edeb07004..f2b4eb57ad555 100644
--- a/flang/test/Lower/CUDA/cuda-device-proc.cuf
+++ b/flang/test/Lower/CUDA/cuda-device-proc.cuf
@@ -152,13 +152,16 @@ end subroutine
 
 attributes(device) subroutine testAtomic()
   integer :: a, istat, j
+  real :: r
   istat = atomicexch(a,0)
+  istat = atomicexch(r, 0.0)
   istat = atomicxor(a, j)
   istat = atomiccas(a, i, 14)
 end subroutine
 
 ! CHECK-LABEL: func.func @_QPtestatomic()
 ! CHECK: llvm.atomicrmw xchg %{{.*}}, %c0{{.*}} seq_cst : !llvm.ptr, i32
+! CHECK: llvm.atomicrmw xchg %{{.*}}, %{{.*}} seq_cst : !llvm.ptr, f32
 ! CHECK: llvm.atomicrmw _xor %{{.*}}, %{{.*}} seq_cst : !llvm.ptr, i32
 ! CHECK: %[[ADDR:.*]] = builtin.unrealized_conversion_cast %{{.*}}#1 : !fir.ref<i32> to !llvm.ptr
 ! CHECK: llvm.cmpxchg %[[ADDR]], %{{.*}}, %c14{{.*}} acq_rel monotonic : !llvm.ptr, i32