[flang-commits] [flang] [flang] Add 32-bit AIX target specific in order to build 32-bit flang-rt (PR #136051)

[Daniel Chen via flang-commits]

https://github.com/DanielCChen created https://github.com/llvm/llvm-project/pull/136051

None

>From 116de4f8b75b8052c4c7ec8e3236b0e47c3d4156 Mon Sep 17 00:00:00 2001
From: Daniel Chen <cdchen at ca.ibm.com>
Date: Wed, 16 Apr 2025 18:53:11 -0400
Subject: [PATCH] [flang] Add 32-bit AIX target specific in order to build
 32-bit flang-rt.

---
 flang/lib/Optimizer/CodeGen/Target.cpp | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp
index e2f8fb9d239a1..374308fa58947 100644
--- a/flang/lib/Optimizer/CodeGen/Target.cpp
+++ b/flang/lib/Optimizer/CodeGen/Target.cpp
@@ -1020,6 +1020,37 @@ struct TargetAArch64 : public GenericTarget<TargetAArch64> {
 };
 } // namespace
 
+//===----------------------------------------------------------------------===//
+// PPC (AIX 32 bit) target specifics.
+//===----------------------------------------------------------------------===//
+namespace {
+struct TargetPPC : public GenericTarget<TargetPPC> {
+  using GenericTarget::GenericTarget;
+
+  static constexpr int defaultWidth = 32;
+
+  CodeGenSpecifics::Marshalling
+  complexArgumentType(mlir::Location, mlir::Type eleTy) const override {
+    CodeGenSpecifics::Marshalling marshal;
+    // two distinct element type arguments (re, im)
+    marshal.emplace_back(eleTy, AT{});
+    marshal.emplace_back(eleTy, AT{});
+    return marshal;
+  }
+
+  CodeGenSpecifics::Marshalling
+  complexReturnType(mlir::Location, mlir::Type eleTy) const override {
+    CodeGenSpecifics::Marshalling marshal;
+    // Use a type that will be translated into LLVM as:
+    // { t, t }   struct of 2 element type
+    marshal.emplace_back(
+        mlir::TupleType::get(eleTy.getContext(), mlir::TypeRange{eleTy, eleTy}),
+        AT{});
+    return marshal;
+  }
+};
+} // namespace
+
 //===----------------------------------------------------------------------===//
 // PPC64 (AIX 64 bit) target specifics.
 //===----------------------------------------------------------------------===//
@@ -1847,6 +1878,9 @@ fir::CodeGenSpecifics::get(mlir::MLIRContext *ctx, llvm::Triple &&trp,
   case llvm::Triple::ArchType::aarch64:
     return std::make_unique<TargetAArch64>(
         ctx, std::move(trp), std::move(kindMap), targetCPU, targetFeatures, dl);
+  case llvm::Triple::ArchType::ppc:
+    return std::make_unique<TargetPPC>(ctx, std::move(trp), std::move(kindMap),
+                                       targetCPU, targetFeatures, dl);
   case llvm::Triple::ArchType::ppc64:
     return std::make_unique<TargetPPC64>(
         ctx, std::move(trp), std::move(kindMap), targetCPU, targetFeatures, dl);