[flang-commits] [clang] [flang] [flang][Driver] Support -print-supported-extensions (PR #117402)
Tarun Prabhu via flang-commits
flang-commits at lists.llvm.org
Fri Nov 22 15:45:15 PST 2024
https://github.com/tarunprabhu created https://github.com/llvm/llvm-project/pull/117402
The implementation is pretty straightforward. The tests mirror those in clang.
>From cd8f7f1cd265b38e5854f42e6141cd0e6160201f Mon Sep 17 00:00:00 2001
From: Tarun Prabhu <tarun.prabhu at gmail.com>
Date: Thu, 21 Nov 2024 11:42:46 -0700
Subject: [PATCH] [flang][Driver] Support -print-supported-extensions
---
clang/include/clang/Driver/Options.td | 8 +-
.../include/flang/Frontend/FrontendOptions.h | 3 +
flang/lib/Frontend/CompilerInvocation.cpp | 2 +
.../print-supported-extensions-aarch64.f90 | 104 +++++++++
.../Driver/print-supported-extensions-arm.f90 | 34 +++
.../print-supported-extensions-riscv.f90 | 211 ++++++++++++++++++
.../Driver/print-supported-extensions.f90 | 10 +
flang/tools/flang-driver/fc1_main.cpp | 46 ++++
8 files changed, 414 insertions(+), 4 deletions(-)
create mode 100644 flang/test/Driver/print-supported-extensions-aarch64.f90
create mode 100644 flang/test/Driver/print-supported-extensions-arm.f90
create mode 100644 flang/test/Driver/print-supported-extensions-riscv.f90
create mode 100644 flang/test/Driver/print-supported-extensions.f90
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 40fd48761928b3..26be300547ad93 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5901,15 +5901,15 @@ def print_supported_cpus : Flag<["-", "--"], "print-supported-cpus">,
"specified,it will print the supported cpus for the default target)">,
MarshallingInfoFlag<FrontendOpts<"PrintSupportedCPUs">>;
+def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">,
+ HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">,
+ MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>;
+
def : Flag<["-"], "mcpu=help">, Alias<print_supported_cpus>;
def : Flag<["-"], "mtune=help">, Alias<print_supported_cpus>;
} // let Visibility = [ClangOption, CC1Option, CLOption, FlangOption, FC1Option]
-def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">,
- Visibility<[ClangOption, CC1Option, CLOption]>,
- HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">,
- MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>;
def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
Visibility<[ClangOption, CC1Option, CLOption]>,
HelpText<"Print the extensions enabled by the given target and -march/-mcpu options."
diff --git a/flang/include/flang/Frontend/FrontendOptions.h b/flang/include/flang/Frontend/FrontendOptions.h
index a4cb021e309d4a..fe833e0af587f0 100644
--- a/flang/include/flang/Frontend/FrontendOptions.h
+++ b/flang/include/flang/Frontend/FrontendOptions.h
@@ -254,6 +254,9 @@ struct FrontendOptions {
/// Print the supported cpus for the current target
unsigned printSupportedCPUs : 1;
+ /// Print the supported extensions for the current target
+ unsigned printSupportedExtensions : 1;
+
/// Enable Provenance to character-stream mapping. Allows e.g. IDEs to find
/// symbols based on source-code location. This is not needed in regular
/// compilation.
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp
index 0b79c95eade0d3..32a79e55989509 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -636,6 +636,8 @@ static bool parseFrontendArgs(FrontendOptions &opts, llvm::opt::ArgList &args,
opts.showVersion = args.hasArg(clang::driver::options::OPT_version);
opts.printSupportedCPUs =
args.hasArg(clang::driver::options::OPT_print_supported_cpus);
+ opts.printSupportedExtensions =
+ args.hasArg(clang::driver::options::OPT_print_supported_extensions);
// Get the input kind (from the value passed via `-x`)
InputKind dashX(Language::Unknown);
diff --git a/flang/test/Driver/print-supported-extensions-aarch64.f90 b/flang/test/Driver/print-supported-extensions-aarch64.f90
new file mode 100644
index 00000000000000..5e5ed0dc0625df
--- /dev/null
+++ b/flang/test/Driver/print-supported-extensions-aarch64.f90
@@ -0,0 +1,104 @@
+! REQUIRES: aarch64-registered-target
+
+! RUN: %flang --target=aarch64-linux-gnu --print-supported-extensions 2>&1 \
+! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+! CHECK: All available -march extensions for AArch64
+! CHECK-EMPTY:
+! CHECK-NEXT: Name Architecture Feature(s) Description
+! CHECK-NEXT: aes FEAT_AES, FEAT_PMULL Enable AES support
+! CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
+! CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
+! CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
+! CHECK-NEXT: cmpbr FEAT_CMPBR Enable Armv9.6-A base compare and branch instructions
+! CHECK-NEXT: fcma FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+! CHECK-NEXT: cpa FEAT_CPA Enable Armv9.5-A Checked Pointer Arithmetic
+! CHECK-NEXT: crc FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+! CHECK-NEXT: crypto FEAT_Crypto Enable cryptographic instructions
+! CHECK-NEXT: cssc FEAT_CSSC Enable Common Short Sequence Compression (CSSC) instructions
+! CHECK-NEXT: d128 FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128 Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions
+! CHECK-NEXT: dit FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+! CHECK-NEXT: dotprod FEAT_DotProd Enable dot product support
+! CHECK-NEXT: f32mm FEAT_F32MM Enable Matrix Multiply FP32 Extension
+! CHECK-NEXT: f64mm FEAT_F64MM Enable Matrix Multiply FP64 Extension
+! CHECK-NEXT: f8f16mm FEAT_F8F16MM Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication
+! CHECK-NEXT: f8f32mm FEAT_F8F32MM Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication
+! CHECK-NEXT: faminmax FEAT_FAMINMAX Enable FAMIN and FAMAX instructions
+! CHECK-NEXT: flagm FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+! CHECK-NEXT: fp FEAT_FP Enable Armv8.0-A Floating Point Extensions
+! CHECK-NEXT: fp16fml FEAT_FHM Enable FP16 FML instructions
+! CHECK-NEXT: fp8 FEAT_FP8 Enable FP8 instructions
+! CHECK-NEXT: fp8dot2 FEAT_FP8DOT2 Enable FP8 2-way dot instructions
+! CHECK-NEXT: fp8dot4 FEAT_FP8DOT4 Enable FP8 4-way dot instructions
+! CHECK-NEXT: fp8fma FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions
+! CHECK-NEXT: fprcvt FEAT_FPRCVT Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes
+! CHECK-NEXT: fp16 FEAT_FP16 Enable half-precision floating-point data processing
+! CHECK-NEXT: gcs FEAT_GCS Enable Armv9.4-A Guarded Call Stack Extension
+! CHECK-NEXT: hbc FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
+! CHECK-NEXT: i8mm FEAT_I8MM Enable Matrix Multiply Int8 Extension
+! CHECK-NEXT: ite FEAT_ITE Enable Armv9.4-A Instrumentation Extension
+! CHECK-NEXT: jscvt FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+! CHECK-NEXT: ls64 FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension
+! CHECK-NEXT: lse FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+! CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions
+! CHECK-NEXT: lsfe FEAT_LSFE Enable Armv9.6-A base Atomic floating-point in-memory instructions
+! CHECK-NEXT: lsui FEAT_LSUI Enable Armv9.6-A unprivileged load/store instructions
+! CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
+! CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
+! CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+! CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
+! CHECK-NEXT: occmo FEAT_OCCMO Enable Armv9.6-A Outer cacheable cache maintenance operations
+! CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+! CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
+! CHECK-NEXT: pcdphint FEAT_PCDPHINT Enable Armv9.6-A Producer Consumer Data Placement hints
+! CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+! CHECK-NEXT: pops FEAT_PoPS Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions
+! CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+! CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions
+! CHECK-NEXT: ras FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+! CHECK-NEXT: rasv2 FEAT_RASv2 Enable Armv8.9-A Reliability, Availability and Serviceability Extensions
+! CHECK-NEXT: rcpc FEAT_LRCPC Enable support for RCPC extension
+! CHECK-NEXT: rcpc3 FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set
+! CHECK-NEXT: rdm FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+! CHECK-NEXT: sb FEAT_SB Enable Armv8.5-A Speculation Barrier
+! CHECK-NEXT: sha2 FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
+! CHECK-NEXT: sha3 FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
+! CHECK-NEXT: sm4 FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
+! CHECK-NEXT: sme FEAT_SME Enable Scalable Matrix Extension (SME)
+! CHECK-NEXT: sme-b16b16 FEAT_SME_B16B16 Enable SME2.1 ZA-targeting non-widening BFloat16 instructions
+! CHECK-NEXT: sme-f16f16 FEAT_SME_F16F16 Enable SME non-widening Float16 instructions
+! CHECK-NEXT: sme-f64f64 FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions
+! CHECK-NEXT: sme-f8f16 FEAT_SME_F8F16 Enable Scalable Matrix Extension (SME) F8F16 instructions
+! CHECK-NEXT: sme-f8f32 FEAT_SME_F8F32 Enable Scalable Matrix Extension (SME) F8F32 instructions
+! CHECK-NEXT: sme-fa64 FEAT_SME_FA64 Enable the full A64 instruction set in streaming SVE mode
+! CHECK-NEXT: sme-i16i64 FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
+! CHECK-NEXT: sme-lutv2 FEAT_SME_LUTv2 Enable Scalable Matrix Extension (SME) LUTv2 instructions
+! CHECK-NEXT: sme2 FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
+! CHECK-NEXT: sme2p1 FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions
+! CHECK-NEXT: sme2p2 FEAT_SME2p2 Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions
+! CHECK-NEXT: profile FEAT_SPE Enable Statistical Profiling extension
+! CHECK-NEXT: predres2 FEAT_SPECRES2 Enable Speculation Restriction Instruction
+! CHECK-NEXT: ssbs FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+! CHECK-NEXT: ssve-aes FEAT_SSVE_AES Enable Armv9.6-A SVE AES support in streaming SVE mode
+! CHECK-NEXT: ssve-fp8dot2 FEAT_SSVE_FP8DOT2 Enable SVE2 FP8 2-way dot product instructions
+! CHECK-NEXT: ssve-fp8dot4 FEAT_SSVE_FP8DOT4 Enable SVE2 FP8 4-way dot product instructions
+! CHECK-NEXT: ssve-fp8fma FEAT_SSVE_FP8FMA Enable SVE2 FP8 multiply-add instructions
+! CHECK-NEXT: sve FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+! CHECK-NEXT: sve-aes FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
+! CHECK-NEXT: sve-aes2 FEAT_SVE_AES2 Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword polynomial multiply instructions
+! CHECK-NEXT: sve-b16b16 FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
+! CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
+! CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
+! CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+! CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes
+! CHECK-NEXT: sve2-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+! CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
+! CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
+! CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
+! CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions
+! CHECK-NEXT: the FEAT_THE Enable Armv8.9-A Translation Hardening Extension
+! CHECK-NEXT: tlbiw FEAT_TLBIW Enable Armv9.5-A TLBI VMALL for Dirty State
+! CHECK-NEXT: tme FEAT_TME Enable Transactional Memory Extension
+! CHECK-NEXT: wfxt FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+
+end program
diff --git a/flang/test/Driver/print-supported-extensions-arm.f90 b/flang/test/Driver/print-supported-extensions-arm.f90
new file mode 100644
index 00000000000000..3e5de541f9a119
--- /dev/null
+++ b/flang/test/Driver/print-supported-extensions-arm.f90
@@ -0,0 +1,34 @@
+! REQUIRES: arm-registered-target
+
+! RUN: %flang --target=arm-linux-gnu --print-supported-extensions 2>&1 \
+! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+! CHECK: All available -march extensions for ARM
+! CHECK-EMPTY:
+! CHECK-NEXT: Name Description
+! CHECK-NEXT: crc Enable support for CRC instructions
+! CHECK-NEXT: crypto Enable support for Cryptography extensions
+! CHECK-NEXT: sha2 Enable SHA1 and SHA256 support
+! CHECK-NEXT: aes Enable AES support
+! CHECK-NEXT: dotprod Enable support for dot product instructions
+! CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb2
+! CHECK-NEXT: mve Support M-Class Vector Extension with integer ops
+! CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops
+! CHECK-NEXT: fp16 Enable half-precision floating point
+! CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions
+! CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions
+! CHECK-NEXT: bf16 Enable support for BFloat16 instructions
+! CHECK-NEXT: sb Enable v8.5a Speculation Barrier
+! CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension
+! CHECK-NEXT: lob Enable Low Overhead Branch extensions
+! CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv1
+! CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv1
+! CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv1
+! CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv1
+! CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv1
+! CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv1
+! CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv1
+! CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv1
+! CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification
+
+end program
diff --git a/flang/test/Driver/print-supported-extensions-riscv.f90 b/flang/test/Driver/print-supported-extensions-riscv.f90
new file mode 100644
index 00000000000000..4bb24e64926ebb
--- /dev/null
+++ b/flang/test/Driver/print-supported-extensions-riscv.f90
@@ -0,0 +1,211 @@
+! REQUIRES: riscv-registered-target
+
+! RUN: %flang --target=riscv64-linux-gnu --print-supported-extensions 2>&1 \
+! RUN: | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+! CHECK: All available -march extensions for RISC-V
+! CHECK-EMPTY:
+! CHECK-NEXT: Name Version Description
+! CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
+! CHECK-NEXT: e 2.0 Implements RV{32,64}E (provides 16 rather than 32 GPRs)
+! CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
+! CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
+! CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
+! CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
+! CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
+! CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
+! CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
+! CHECK-NEXT: h 1.0 'H' (Hypervisor)
+! CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes)
+! CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions)
+! CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
+! CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
+! CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
+! CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
+! CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
+! CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
+! CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
+! CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
+! CHECK-NEXT: zicsr 2.0 'zicsr' (CSRs)
+! CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
+! CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
+! CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
+! CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters)
+! CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations)
+! CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
+! CHECK-NEXT: za128rs 1.0 'Za128rs' (Reservation Set Size of at Most 128 Bytes)
+! CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes)
+! CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
+! CHECK-NEXT: zabha 1.0 'Zabha' (Byte and Halfword Atomic Memory Operations)
+! CHECK-NEXT: zacas 1.0 'Zacas' (Atomic Compare-And-Swap Instructions)
+! CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
+! CHECK-NEXT: zama16b 1.0 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)
+! CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set)
+! CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point)
+! CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts)
+! CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point)
+! CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal)
+! CHECK-NEXT: zfinx 1.0 'Zfinx' (Float in Integer)
+! CHECK-NEXT: zdinx 1.0 'Zdinx' (Double in Integer)
+! CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
+! CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions)
+! CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
+! CHECK-NEXT: zce 1.0 'Zce' (Compressed extensions for microcontrollers)
+! CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
+! CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations)
+! CHECK-NEXT: zcmp 1.0 'Zcmp' (sequenced instructions for code-size reduction)
+! CHECK-NEXT: zcmt 1.0 'Zcmt' (table jump instructions for code-size reduction)
+! CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
+! CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
+! CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
+! CHECK-NEXT: zbkb 1.0 'Zbkb' (Bitmanip instructions for Cryptography)
+! CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply instructions for Cryptography)
+! CHECK-NEXT: zbkx 1.0 'Zbkx' (Crossbar permutation instructions)
+! CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
+! CHECK-NEXT: zk 1.0 'Zk' (Standard scalar cryptography extension)
+! CHECK-NEXT: zkn 1.0 'Zkn' (NIST Algorithm Suite)
+! CHECK-NEXT: zknd 1.0 'Zknd' (NIST Suite: AES Decryption)
+! CHECK-NEXT: zkne 1.0 'Zkne' (NIST Suite: AES Encryption)
+! CHECK-NEXT: zknh 1.0 'Zknh' (NIST Suite: Hash Function Instructions)
+! CHECK-NEXT: zkr 1.0 'Zkr' (Entropy Source Extension)
+! CHECK-NEXT: zks 1.0 'Zks' (ShangMi Algorithm Suite)
+! CHECK-NEXT: zksed 1.0 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)
+! CHECK-NEXT: zksh 1.0 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)
+! CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency)
+! CHECK-NEXT: ztso 1.0 'Ztso' (Memory Model - Total Store Order)
+! CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions)
+! CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication)
+! CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
+! CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
+! CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
+! CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
+! CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
+! CHECK-NEXT: zvfbfmin 1.0 'Zvbfmin' (Vector BF16 Converts)
+! CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
+! CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
+! CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
+! CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography)
+! CHECK-NEXT: zvkg 1.0 'Zvkg' (Vector GCM instructions for Cryptography)
+! CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')
+! CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')
+! CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round))
+! CHECK-NEXT: zvkng 1.0 'zvkng' (shorthand for 'Zvkn' and 'Zvkg')
+! CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only))
+! CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))
+! CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')
+! CHECK-NEXT: zvksc 1.0 'Zvksc' (shorthand for 'Zvks' and 'Zvbc')
+! CHECK-NEXT: zvksed 1.0 'Zvksed' (SM4 Block Cipher Instructions)
+! CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for 'Zvks' and 'Zvkg')
+! CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function Instructions)
+! CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
+! CHECK-NEXT: zvl1024b 1.0 'Zvl' (Minimum Vector Length) 1024
+! CHECK-NEXT: zvl128b 1.0 'Zvl' (Minimum Vector Length) 128
+! CHECK-NEXT: zvl16384b 1.0 'Zvl' (Minimum Vector Length) 16384
+! CHECK-NEXT: zvl2048b 1.0 'Zvl' (Minimum Vector Length) 2048
+! CHECK-NEXT: zvl256b 1.0 'Zvl' (Minimum Vector Length) 256
+! CHECK-NEXT: zvl32768b 1.0 'Zvl' (Minimum Vector Length) 32768
+! CHECK-NEXT: zvl32b 1.0 'Zvl' (Minimum Vector Length) 32
+! CHECK-NEXT: zvl4096b 1.0 'Zvl' (Minimum Vector Length) 4096
+! CHECK-NEXT: zvl512b 1.0 'Zvl' (Minimum Vector Length) 512
+! CHECK-NEXT: zvl64b 1.0 'Zvl' (Minimum Vector Length) 64
+! CHECK-NEXT: zvl65536b 1.0 'Zvl' (Minimum Vector Length) 65536
+! CHECK-NEXT: zvl8192b 1.0 'Zvl' (Minimum Vector Length) 8192
+! CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
+! CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
+! CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
+! CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
+! CHECK-NEXT: shgatpa 1.0 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
+! CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
+! CHECK-NEXT: shvsatpa 1.0 'Svsatpa' (vsatp supports all modes supported by satp)
+! CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)
+! CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
+! CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
+! CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
+! CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
+! CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
+! CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
+! CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
+! CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
+! CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts)
+! CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
+! CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
+! CHECK-NEXT: ssccfg 1.0 'Ssccfg' (Counter Configuration Supervisor Level)
+! CHECK-NEXT: ssccptr 1.0 'Ssccptr' (Main memory supports page table reads)
+! CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
+! CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
+! CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
+! CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
+! CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
+! CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
+! CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
+! CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
+! CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
+! CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
+! CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values)
+! CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode)
+! CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported)
+! CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
+! CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
+! CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
+! CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
+! CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
+! CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
+! CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
+! CHECK-NEXT: svvptc 1.0 'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
+! CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
+! CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
+! CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)
+! CHECK-NEXT: xcvelw 1.0 'XCVelw' (CORE-V Event Load Word)
+! CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
+! CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
+! CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
+! CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
+! CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)
+! CHECK-NEXT: xsfvfnrclipxfqf 1.0 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)
+! CHECK-NEXT: xsfvfwmaccqqq 1.0 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))
+! CHECK-NEXT: xsfvqmaccdod 1.0 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))
+! CHECK-NEXT: xsfvqmaccqoq 1.0 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
+! CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
+! CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
+! CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions)
+! CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions)
+! CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions)
+! CHECK-NEXT: xtheadcmo 1.0 'XTHeadCmo' (T-Head cache management instructions)
+! CHECK-NEXT: xtheadcondmov 1.0 'XTHeadCondMov' (T-Head conditional move instructions)
+! CHECK-NEXT: xtheadfmemidx 1.0 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)
+! CHECK-NEXT: xtheadmac 1.0 'XTHeadMac' (T-Head Multiply-Accumulate Instructions)
+! CHECK-NEXT: xtheadmemidx 1.0 'XTHeadMemIdx' (T-Head Indexed Memory Operations)
+! CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations)
+! CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions)
+! CHECK-NEXT: xtheadvdot 1.0 'XTHeadVdot' (T-Head Vector Extensions for Dot)
+! CHECK-NEXT: xventanacondops 1.0 'XVentanaCondOps' (Ventana Conditional Ops)
+! CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes)
+! CHECK-EMPTY:
+! CHECK-NEXT: Experimental extensions
+! CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
+! CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
+! CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
+! CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
+! CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
+! CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
+! CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
+! CHECK-EMPTY:
+! CHECK-NEXT: Supported Profiles
+! CHECK-NEXT: rva20s64
+! CHECK-NEXT: rva20u64
+! CHECK-NEXT: rva22s64
+! CHECK-NEXT: rva22u64
+! CHECK-NEXT: rva23s64
+! CHECK-NEXT: rva23u64
+! CHECK-NEXT: rvb23s64
+! CHECK-NEXT: rvb23u64
+! CHECK-NEXT: rvi20u32
+! CHECK-NEXT: rvi20u64
+! CHECK-EMPTY:
+! CHECK-NEXT: Experimental Profiles
+! CHECK-NEXT: rvm23u32
+! CHECK-EMPTY:
+! CHECK-NEXT: Use -march to specify the target's extension.
+! CHECK-NEXT: For example, clang -march=rv32i_v1p0
+
+end program
diff --git a/flang/test/Driver/print-supported-extensions.f90 b/flang/test/Driver/print-supported-extensions.f90
new file mode 100644
index 00000000000000..4a854d276c30b6
--- /dev/null
+++ b/flang/test/Driver/print-supported-extensions.f90
@@ -0,0 +1,10 @@
+! Test that --print-supported-extensions errors on unsupported architectures.
+
+! REQUIRES: x86-registered-target
+
+! RUN: not %flang --target=x86_64-linux-gnu --print-supported-extensions \
+! RUN: 2>&1 | FileCheck %s
+
+! CHECK: error: option '--print-supported-extensions' cannot be specified on this target
+
+end program
diff --git a/flang/tools/flang-driver/fc1_main.cpp b/flang/tools/flang-driver/fc1_main.cpp
index 561a0dd5524e37..cc57acdecf7aa2 100644
--- a/flang/tools/flang-driver/fc1_main.cpp
+++ b/flang/tools/flang-driver/fc1_main.cpp
@@ -21,12 +21,16 @@
#include "flang/Frontend/TextDiagnosticBuffer.h"
#include "flang/FrontendTool/Utils.h"
#include "clang/Driver/DriverDiagnostic.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Option/Arg.h"
#include "llvm/Option/ArgList.h"
#include "llvm/Option/OptTable.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/ARMTargetParser.h"
+#include "llvm/TargetParser/RISCVISAInfo.h"
#include <cstdio>
@@ -50,6 +54,43 @@ static int printSupportedCPUs(llvm::StringRef triple) {
return 0;
}
+static int printSupportedExtensions(std::string triple) {
+ std::string error;
+ const llvm::Target *target =
+ llvm::TargetRegistry::lookupTarget(triple, error);
+ if (!target) {
+ llvm::errs() << error;
+ return 1;
+ }
+
+ llvm::TargetOptions targetOpts;
+ std::unique_ptr<llvm::TargetMachine> targetMachine(
+ target->createTargetMachine(triple, "", "", targetOpts, std::nullopt));
+ const llvm::Triple &targetTriple = targetMachine->getTargetTriple();
+ const llvm::MCSubtargetInfo *mcInfo = targetMachine->getMCSubtargetInfo();
+ const llvm::ArrayRef<llvm::SubtargetFeatureKV> features =
+ mcInfo->getAllProcessorFeatures();
+
+ llvm::StringMap<llvm::StringRef> descMap;
+ for (const llvm::SubtargetFeatureKV &feature : features)
+ descMap.insert({feature.Key, feature.Desc});
+
+ if (targetTriple.isRISCV())
+ llvm::RISCVISAInfo::printSupportedExtensions(descMap);
+ else if (targetTriple.isAArch64())
+ llvm::AArch64::PrintSupportedExtensions();
+ else if (targetTriple.isARM())
+ llvm::ARM::PrintSupportedExtensions(descMap);
+ else {
+ // The option was already checked in Driver::HandleImmediateArgs,
+ // so we do not expect to get here if we are not a supported architecture.
+ assert(0 && "Unhandled triple for --print-supported-extensions option.");
+ return 1;
+ }
+
+ return 0;
+}
+
int fc1_main(llvm::ArrayRef<const char *> argv, const char *argv0) {
// Create CompilerInstance
std::unique_ptr<CompilerInstance> flang(new CompilerInstance());
@@ -82,6 +123,11 @@ int fc1_main(llvm::ArrayRef<const char *> argv, const char *argv0) {
if (flang->getFrontendOpts().printSupportedCPUs)
return printSupportedCPUs(flang->getInvocation().getTargetOpts().triple);
+ // --print-supported-extensions takes priority over the actual compilation.
+ if (flang->getFrontendOpts().printSupportedExtensions)
+ return printSupportedExtensions(
+ flang->getInvocation().getTargetOpts().triple);
+
diagsBuffer->flushDiagnostics(flang->getDiagnostics());
if (!success)
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