[flang-commits] [libcxx] [clang] [clang-tools-extra] [llvm] [compiler-rt] [libc] [flang] [X86] Support promoted ENQCMD, KEYLOCKER and USERMSR (PR #77293)
via flang-commits
flang-commits at lists.llvm.org
Thu Jan 25 19:00:12 PST 2024
https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/77293
>From de38a9019c581251e60d4e4e5651e33c65920edf Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 8 Jan 2024 00:02:26 -0800
Subject: [PATCH 01/13] [X86] Support AMX promoted keylocker and enqcmd
instructions
---
.../Support/X86DisassemblerDecoderCommon.h | 2 +
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 18 +-
llvm/lib/Target/X86/X86InstrKL.td | 96 ++++++-----
llvm/lib/Target/X86/X86InstrMisc.td | 24 ++-
llvm/test/CodeGen/X86/enqcmd-intrinsics.ll | 13 ++
.../X86/keylocker-intrinsics-fast-isel.ll | 154 ++++++++++++++++++
llvm/test/MC/Disassembler/X86/apx/enqcmd.txt | 18 ++
.../MC/Disassembler/X86/apx/keylocker.txt | 82 ++++++++++
llvm/test/MC/X86/apx/enqcmd-att.s | 20 +++
llvm/test/MC/X86/apx/enqcmd-intel.s | 17 ++
llvm/test/MC/X86/apx/keylocker-att.s | 84 ++++++++++
llvm/test/MC/X86/apx/keylocker-intel.s | 81 +++++++++
llvm/utils/TableGen/X86DisassemblerTables.cpp | 8 +-
llvm/utils/TableGen/X86RecognizableInstr.cpp | 15 +-
14 files changed, 579 insertions(+), 53 deletions(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
create mode 100644 llvm/test/MC/Disassembler/X86/apx/keylocker.txt
create mode 100644 llvm/test/MC/X86/apx/enqcmd-att.s
create mode 100644 llvm/test/MC/X86/apx/enqcmd-intel.s
create mode 100644 llvm/test/MC/X86/apx/keylocker-att.s
create mode 100644 llvm/test/MC/X86/apx/keylocker-intel.s
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 3aceb247a26c21e..0dc974ea9efd8d1 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -140,7 +140,9 @@ enum attributeBits {
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
+ ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
+ ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 833f058253d880d..679382fcf438c93 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5035,14 +5035,16 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
- case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
- case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
+#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
+ case Intrinsic::x86_encodekey128: Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128); break;
+ case Intrinsic::x86_encodekey256: Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256); break;
+#undef GET_EGPR_IF_ENABLED
}
SDValue Chain = Node->getOperand(0);
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM0, Node->getOperand(3),
SDValue());
- if (Opcode == X86::ENCODEKEY256)
+ if (Opcode == X86::ENCODEKEY256 || Opcode == X86::ENCODEKEY256_EVEX)
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM1, Node->getOperand(4),
Chain.getValue(1));
@@ -6393,18 +6395,20 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
switch (Node->getOpcode()) {
default:
llvm_unreachable("Unexpected opcode!");
+#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
case X86ISD::AESENCWIDE128KL:
- Opcode = X86::AESENCWIDE128KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
break;
case X86ISD::AESDECWIDE128KL:
- Opcode = X86::AESDECWIDE128KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE128KL);
break;
case X86ISD::AESENCWIDE256KL:
- Opcode = X86::AESENCWIDE256KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE256KL);
break;
case X86ISD::AESDECWIDE256KL:
- Opcode = X86::AESDECWIDE256KL;
+ Opcode = GET_EGPR_IF_ENABLED(X86::AESDECWIDE256KL);
break;
+#undef GET_EGPR_IF_ENABLED
}
SDValue Chain = Node->getOperand(0);
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 4586fc541627fe9..5dfd5e7493128bd 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -14,61 +14,83 @@
//===----------------------------------------------------------------------===//
// Key Locker instructions
+class Encodekey<bits<8> opcode, string mnemonic>
+ : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), mnemonic#"\t{$src, $dst|$dst, $src}", []>,
+ NoCD8, XS;
-let SchedRW = [WriteSystem], Predicates = [HasKL] in {
- let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
+class Aesencdec<bits<8> opcode, string mnemonic, SDNode node>
+ : I<opcode, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
+ mnemonic#"\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (node VR128:$src1, addr:$src2))]>, NoCD8, XS;
+
+let SchedRW = [WriteSystem] in {
+ let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
"loadiwkey\t{$src2, $src1|$src1, $src2}",
[(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8, XS;
}
+ let Predicates = [HasKL, NoEGPR] in {
let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
- "encodekey128\t{$src, $dst|$dst, $src}", []>, T8, XS;
+ def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
}
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
- "encodekey256\t{$src, $dst|$dst, $src}", []>, T8, XS;
+ def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
}
- let Constraints = "$src1 = $dst",
- Defs = [EFLAGS] in {
- def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesenc128kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8, XS;
-
- def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesdec128kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8, XS;
-
- def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesenc256kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8, XS;
-
- def AESDEC256KL : I<0xDF, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- "aesdec256kl\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS,
- (X86aesdec256kl VR128:$src1, addr:$src2))]>, T8, XS;
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in {
+ def AESENC128KL : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, T8;
+
+ def AESDEC128KL : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, T8;
+
+ def AESENC256KL : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, T8;
+
+ def AESDEC256KL : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, T8;
+ }
}
-} // SchedRW, Predicates
+ let Predicates = [HasKL, HasEGPR, In64BitMode] in {
+ let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
+ def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
+ }
+
+ let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
+ def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
+ }
-let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in {
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
+ def AESENC128KL_EVEX : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, EVEX, T_MAP4;
+
+ def AESDEC128KL_EVEX : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, EVEX, T_MAP4;
+
+ def AESENC256KL_EVEX : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, EVEX, T_MAP4;
+
+ def AESDEC256KL_EVEX : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, EVEX, T_MAP4;
+ }
+ }
+} // SchedRW
+
+class Aesencdecwide<bits<8> opcode, Format f, string mnemonic>
+ : I<opcode, f, (outs), (ins opaquemem:$src), mnemonic#"\t$src", []>, NoCD8, XS;
+
+let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
mayLoad = 1 in {
- def AESENCWIDE128KL : I<0xD8, MRM0m, (outs), (ins opaquemem:$src),
- "aesencwide128kl\t$src", []>, T8, XS;
- def AESDECWIDE128KL : I<0xD8, MRM1m, (outs), (ins opaquemem:$src),
- "aesdecwide128kl\t$src", []>, T8, XS;
- def AESENCWIDE256KL : I<0xD8, MRM2m, (outs), (ins opaquemem:$src),
- "aesencwide256kl\t$src", []>, T8, XS;
- def AESDECWIDE256KL : I<0xD8, MRM3m, (outs), (ins opaquemem:$src),
- "aesdecwide256kl\t$src", []>, T8, XS;
+ let Predicates = [HasWIDEKL, NoEGPR] in {
+ def AESENCWIDE128KL : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, T8;
+ def AESDECWIDE128KL : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, T8;
+ def AESENCWIDE256KL : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, T8;
+ def AESDECWIDE256KL : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, T8;
+ }
+
+ let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in {
+ def AESENCWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, EVEX, T_MAP4;
+ def AESDECWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, EVEX, T_MAP4;
+ def AESENCWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, EVEX, T_MAP4;
+ def AESDECWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, EVEX, T_MAP4;
+ }
}
} // SchedRW, Predicates
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 66fac2369d0a918..250325577c7af5a 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1569,7 +1569,7 @@ let SchedRW = [WriteStore], Defs = [EFLAGS] in {
def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
"enqcmd\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
- T8, XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
+ T8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
"enqcmds\t{$src, $dst|$dst, $src}",
@@ -1582,7 +1582,27 @@ let SchedRW = [WriteStore], Defs = [EFLAGS] in {
def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
"enqcmds\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
- T8, XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
+ T8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
+
+let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in {
+ def ENQCMD32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
+ EVEX, NoCD8, T_MAP4, XD, AdSize32;
+ def ENQCMD64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
+ EVEX, NoCD8, T_MAP4, XD, AdSize64;
+
+ def ENQCMDS32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
+ EVEX, NoCD8, T_MAP4, XS, AdSize32;
+ def ENQCMDS64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
+ EVEX, NoCD8, T_MAP4, XS, AdSize64;
+}
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
index e5a6d2ead72d369..230a2ffc059413a 100644
--- a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+enqcmd | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
define i8 @test_enqcmd(ptr %dst, ptr %src) {
; X64-LABEL: test_enqcmd:
@@ -23,6 +24,12 @@ define i8 @test_enqcmd(ptr %dst, ptr %src) {
; X32-NEXT: enqcmd (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+;
+; EGPR-LABEL: test_enqcmd:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: enqcmd (%rsi), %rdi # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0x3e]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
@@ -50,6 +57,12 @@ define i8 @test_enqcmds(ptr %dst, ptr %src) {
; X32-NEXT: enqcmds (%esi), %edi
; X32-NEXT: sete %al
; X32-NEXT: retq
+;
+; EGPR-LABEL: test_enqcmds:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: enqcmds (%rsi), %rdi # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0x3e]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
index 78eecdaf29e2cb1..1d90d1c31d5ca89 100644
--- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl | FileCheck %s
+; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+kl,+widekl,+egpr --show-mc-encoding | FileCheck %s --check-prefix=EGPR
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/X86/keylocker-builtins.c
@@ -9,6 +10,12 @@ define void @test_loadiwkey(i32 %ctl, <2 x i64> %intkey, <2 x i64> %enkey_lo, <2
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: loadiwkey %xmm2, %xmm1
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_loadiwkey:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movl %edi, %eax # encoding: [0x89,0xf8]
+; EGPR-NEXT: loadiwkey %xmm2, %xmm1 # encoding: [0xf3,0x0f,0x38,0xdc,0xca]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
tail call void @llvm.x86.loadiwkey(<2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi, i32 %ctl)
ret void
@@ -25,6 +32,17 @@ define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, ptr nocapture %h)
; CHECK-NEXT: movups %xmm5, 64(%rsi)
; CHECK-NEXT: movups %xmm6, 80(%rsi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_encodekey128_u32:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: encodekey128 %edi, %eax # encoding: [0x62,0xf4,0x7e,0x08,0xda,0xc7]
+; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
+; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
+; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
+; EGPR-NEXT: movups %xmm4, 48(%rsi) # encoding: [0x0f,0x11,0x66,0x30]
+; EGPR-NEXT: movups %xmm5, 64(%rsi) # encoding: [0x0f,0x11,0x6e,0x40]
+; EGPR-NEXT: movups %xmm6, 80(%rsi) # encoding: [0x0f,0x11,0x76,0x50]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %htype, <2 x i64> %key)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -60,6 +78,18 @@ define i32 @test_encodekey256_u32(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_
; CHECK-NEXT: movups %xmm5, 80(%rsi)
; CHECK-NEXT: movups %xmm6, 96(%rsi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_encodekey256_u32:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: encodekey256 %edi, %eax # encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xc7]
+; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
+; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
+; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
+; EGPR-NEXT: movups %xmm3, 48(%rsi) # encoding: [0x0f,0x11,0x5e,0x30]
+; EGPR-NEXT: movups %xmm4, 64(%rsi) # encoding: [0x0f,0x11,0x66,0x40]
+; EGPR-NEXT: movups %xmm5, 80(%rsi) # encoding: [0x0f,0x11,0x6e,0x50]
+; EGPR-NEXT: movups %xmm6, 96(%rsi) # encoding: [0x0f,0x11,0x76,0x60]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_hi)
%1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
@@ -94,6 +124,14 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesenc256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xde,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -110,6 +148,14 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesdec256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdf,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -126,6 +172,14 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesenc128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdc,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -142,6 +196,14 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; CHECK-NEXT: sete %al
; CHECK-NEXT: movaps %xmm0, (%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test_mm_aesdec128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdd,0x06]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = tail call { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64> %idata, ptr %h) #1
%1 = extractvalue { i8, <2 x i64> } %0, 1
@@ -173,6 +235,29 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesencwide128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesencwide128kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x02]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -240,6 +325,29 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesdecwide128kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdecwide128kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x0a]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -307,6 +415,29 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesencwide256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesencwide256kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x12]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
@@ -374,6 +505,29 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
; CHECK-NEXT: retq
+;
+; EGPR-LABEL: test__mm_aesdecwide256kl_u8:
+; EGPR: # %bb.0: # %entry
+; EGPR-NEXT: movaps (%rsi), %xmm0 # encoding: [0x0f,0x28,0x06]
+; EGPR-NEXT: movaps 16(%rsi), %xmm1 # encoding: [0x0f,0x28,0x4e,0x10]
+; EGPR-NEXT: movaps 32(%rsi), %xmm2 # encoding: [0x0f,0x28,0x56,0x20]
+; EGPR-NEXT: movaps 48(%rsi), %xmm3 # encoding: [0x0f,0x28,0x5e,0x30]
+; EGPR-NEXT: movaps 64(%rsi), %xmm4 # encoding: [0x0f,0x28,0x66,0x40]
+; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50]
+; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
+; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
+; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
+; EGPR-NEXT: aesdecwide256kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x1a]
+; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
+; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
+; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
+; EGPR-NEXT: movaps %xmm2, 32(%rdi) # encoding: [0x0f,0x29,0x57,0x20]
+; EGPR-NEXT: movaps %xmm3, 48(%rdi) # encoding: [0x0f,0x29,0x5f,0x30]
+; EGPR-NEXT: movaps %xmm4, 64(%rdi) # encoding: [0x0f,0x29,0x67,0x40]
+; EGPR-NEXT: movaps %xmm5, 80(%rdi) # encoding: [0x0f,0x29,0x6f,0x50]
+; EGPR-NEXT: movaps %xmm6, 96(%rdi) # encoding: [0x0f,0x29,0x77,0x60]
+; EGPR-NEXT: movaps %xmm7, 112(%rdi) # encoding: [0x0f,0x29,0x7f,0x70]
+; EGPR-NEXT: retq # encoding: [0xc3]
entry:
%0 = load <2 x i64>, ptr %idata, align 16
%1 = getelementptr <2 x i64>, ptr %idata, i64 1
diff --git a/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
new file mode 100644
index 000000000000000..11e7a6cf0e10fbf
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: enqcmd 123(%eax,%ebx,4), %ecx
+# INTEL: enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmd 123(%rax,%rbx,4), %r9
+# INTEL: enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmd 291(%r28d,%r29d,4), %r18d
+# INTEL: enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: enqcmd 291(%r28,%r29,4), %r19
+# INTEL: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
new file mode 100644
index 000000000000000..d74aa4886575dfb
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
@@ -0,0 +1,82 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: aesdec128kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesdec128kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b
+
+# ATT: aesdec128kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesdec128kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesdec256kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesdec256kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b
+
+# ATT: aesdec256kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesdec256kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesdecwide128kl 123(%rax,%rbx,4)
+# INTEL: aesdecwide128kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b
+
+# ATT: aesdecwide128kl 291(%r28,%r29,4)
+# INTEL: aesdecwide128kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesdecwide256kl 123(%rax,%rbx,4)
+# INTEL: aesdecwide256kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b
+
+# ATT: aesdecwide256kl 291(%r28,%r29,4)
+# INTEL: aesdecwide256kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesenc128kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesenc128kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b
+
+# ATT: aesenc128kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesenc128kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesenc256kl 123(%rax,%rbx,4), %xmm12
+# INTEL: aesenc256kl xmm12, [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b
+
+# ATT: aesenc256kl 291(%r28,%r29,4), %xmm12
+# INTEL: aesenc256kl xmm12, [r28 + 4*r29 + 291]
+0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesencwide128kl 123(%rax,%rbx,4)
+# INTEL: aesencwide128kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b
+
+# ATT: aesencwide128kl 291(%r28,%r29,4)
+# INTEL: aesencwide128kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00
+
+# ATT: aesencwide256kl 123(%rax,%rbx,4)
+# INTEL: aesencwide256kl [rax + 4*rbx + 123]
+0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b
+
+# ATT: aesencwide256kl 291(%r28,%r29,4)
+# INTEL: aesencwide256kl [r28 + 4*r29 + 291]
+0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: encodekey128 %ecx, %edx
+# INTEL: encodekey128 edx, ecx
+0x62,0xf4,0x7e,0x08,0xda,0xd1
+
+# ATT: encodekey128 %r18d, %r22d
+# INTEL: encodekey128 r22d, r18d
+0x62,0xec,0x7e,0x08,0xda,0xf2
+
+# ATT: encodekey256 %ecx, %edx
+# INTEL: encodekey256 edx, ecx
+0x62,0xf4,0x7e,0x08,0xdb,0xd1
+
+# ATT: encodekey256 %r18d, %r22d
+# INTEL: encodekey256 r22d, r18d
+0x62,0xec,0x7e,0x08,0xdb,0xf2
diff --git a/llvm/test/MC/X86/apx/enqcmd-att.s b/llvm/test/MC/X86/apx/enqcmd-att.s
new file mode 100644
index 000000000000000..5716883edb18542
--- /dev/null
+++ b/llvm/test/MC/X86/apx/enqcmd-att.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-4: error:
+# ERROR-NOT: error:
+# CHECK: {evex} enqcmd 123(%eax,%ebx,4), %ecx
+# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd 123(%eax,%ebx,4), %ecx
+
+# CHECK: {evex} enqcmd 123(%rax,%rbx,4), %r9
+# CHECK: encoding: [0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd 123(%rax,%rbx,4), %r9
+
+# CHECK: enqcmd 291(%r28d,%r29d,4), %r18d
+# CHECK: encoding: [0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmd 291(%r28d,%r29d,4), %r18d
+
+# CHECK: enqcmd 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmd 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/enqcmd-intel.s b/llvm/test/MC/X86/apx/enqcmd-intel.s
new file mode 100644
index 000000000000000..3b176f11cd56d9c
--- /dev/null
+++ b/llvm/test/MC/X86/apx/enqcmd-intel.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: {evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
+
+# CHECK: {evex} enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmd r9, zmmword ptr [rax + 4*rbx + 123]
+
+# CHECK: enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+# CHECK: encoding: [0x67,0x62,0x8c,0x7b,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmd r18d, zmmword ptr [r28d + 4*r29d + 291]
+
+# CHECK: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/keylocker-att.s b/llvm/test/MC/X86/apx/keylocker-att.s
new file mode 100644
index 000000000000000..101c26f4a0459aa
--- /dev/null
+++ b/llvm/test/MC/X86/apx/keylocker-att.s
@@ -0,0 +1,84 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-20: error:
+# ERROR-NOT: error:
+# CHECK: {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
+ {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesdec128kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec128kl 291(%r28,%r29,4), %xmm12
+
+# CHECK: {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
+ {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesdec256kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec256kl 291(%r28,%r29,4), %xmm12
+
+# CHECK: {evex} aesdecwide128kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
+ {evex} aesdecwide128kl 123(%rax,%rbx,4)
+
+# CHECK: aesdecwide128kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide128kl 291(%r28,%r29,4)
+
+# CHECK: {evex} aesdecwide256kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
+ {evex} aesdecwide256kl 123(%rax,%rbx,4)
+
+# CHECK: aesdecwide256kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide256kl 291(%r28,%r29,4)
+
+# CHECK: {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
+ {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesenc128kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc128kl 291(%r28,%r29,4), %xmm12
+
+# CHECK: {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
+ {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
+
+# CHECK: aesenc256kl 291(%r28,%r29,4), %xmm12
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc256kl 291(%r28,%r29,4), %xmm12
+
+# CHECK: {evex} aesencwide128kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
+ {evex} aesencwide128kl 123(%rax,%rbx,4)
+
+# CHECK: aesencwide128kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
+ aesencwide128kl 291(%r28,%r29,4)
+
+# CHECK: {evex} aesencwide256kl 123(%rax,%rbx,4)
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
+ {evex} aesencwide256kl 123(%rax,%rbx,4)
+
+# CHECK: aesencwide256kl 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
+ aesencwide256kl 291(%r28,%r29,4)
+
+# CHECK: {evex} encodekey128 %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
+ {evex} encodekey128 %ecx, %edx
+
+# CHECK: encodekey128 %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
+ encodekey128 %r18d, %r22d
+
+# CHECK: {evex} encodekey256 %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
+ {evex} encodekey256 %ecx, %edx
+
+# CHECK: encodekey256 %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
+ encodekey256 %r18d, %r22d
diff --git a/llvm/test/MC/X86/apx/keylocker-intel.s b/llvm/test/MC/X86/apx/keylocker-intel.s
new file mode 100644
index 000000000000000..92c93f43af0b994
--- /dev/null
+++ b/llvm/test/MC/X86/apx/keylocker-intel.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
+ {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesdec128kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec128kl xmm12, [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
+ {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesdec256kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesdec256kl xmm12, [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesdecwide128kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
+ {evex} aesdecwide128kl [rax + 4*rbx + 123]
+
+# CHECK: aesdecwide128kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide128kl [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesdecwide256kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
+ {evex} aesdecwide256kl [rax + 4*rbx + 123]
+
+# CHECK: aesdecwide256kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ aesdecwide256kl [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
+ {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesenc128kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc128kl xmm12, [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
+ {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
+
+# CHECK: aesenc256kl xmm12, [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
+ aesenc256kl xmm12, [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesencwide128kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
+ {evex} aesencwide128kl [rax + 4*rbx + 123]
+
+# CHECK: aesencwide128kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
+ aesencwide128kl [r28 + 4*r29 + 291]
+
+# CHECK: {evex} aesencwide256kl [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
+ {evex} aesencwide256kl [rax + 4*rbx + 123]
+
+# CHECK: aesencwide256kl [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
+ aesencwide256kl [r28 + 4*r29 + 291]
+
+# CHECK: {evex} encodekey128 edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
+ {evex} encodekey128 edx, ecx
+
+# CHECK: encodekey128 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
+ encodekey128 r22d, r18d
+
+# CHECK: {evex} encodekey256 edx, ecx
+# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
+ {evex} encodekey256 edx, ecx
+
+# CHECK: encodekey256 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xdb,0xf2]
+ encodekey256 r22d, r18d
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 9ee1472bdf5cc1b..23886a3468243e5 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -214,6 +214,8 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
case IC_EVEX_OPSIZE_ADSIZE:
+ case IC_EVEX_XS_ADSIZE:
+ case IC_EVEX_XD_ADSIZE:
return false;
case IC_EVEX_K:
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
@@ -894,8 +896,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
for (unsigned index = 0; index < ATTR_max; ++index) {
o.indent(i * 2);
- if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+ if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
o << "IC_EVEX_OPSIZE_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
+ o << "IC_EVEX_XD_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
+ o << "IC_EVEX_XS_ADSIZE";
else if (index & ATTR_EVEXNF) {
o << "IC_EVEX";
if (index & ATTR_REXW)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index fb430676c504b9f..c2032e576dd087e 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -168,6 +168,11 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
void RecognizableInstr::processInstr(DisassemblerTables &tables,
const CodeGenInstruction &insn,
InstrUID uid) {
+ if (insn.TheDef->getName() == "ENQCMD32_EVEX")
+ {
+ if (insn.TheDef->getName() == "yikarus")
+ return;
+ }
if (!insn.TheDef->isSubClassOf("X86Inst"))
return;
RecognizableInstr recogInstr(tables, insn, uid);
@@ -188,6 +193,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
#define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
#define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
+#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -277,14 +283,11 @@ InstructionContext RecognizableInstr::insnContext() const {
}
// No L, no W
else if (OpPrefix == X86Local::PD) {
- if (AdSize == X86Local::AdSize32)
- insnContext = IC_EVEX_OPSIZE_ADSIZE;
- else
- insnContext = EVEX_KB(IC_EVEX_OPSIZE);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
} else if (OpPrefix == X86Local::XD)
- insnContext = EVEX_KB(IC_EVEX_XD);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
else if (OpPrefix == X86Local::XS)
- insnContext = EVEX_KB(IC_EVEX_XS);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB(IC_EVEX);
else {
>From 5deb1b43951d038fdcfcd02faf7a9e8d7957933a Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 8 Jan 2024 02:13:47 -0800
Subject: [PATCH 02/13] support urdmsr
---
.../X86/Disassembler/X86Disassembler.cpp | 3 ++
llvm/lib/Target/X86/X86InstrSystem.td | 20 ++++++++-
llvm/test/CodeGen/X86/usermsr-intrinsics.ll | 35 ++++++++++++++++
llvm/test/MC/Disassembler/X86/apx/enqcmd.txt | 20 +++++++++
.../MC/Disassembler/X86/apx/keylocker.txt | 20 +++++++++
.../test/MC/Disassembler/X86/apx/user-msr.txt | 38 +++++++++++++++++
llvm/test/MC/X86/apx/enqcmd-att.s | 23 ++++++++++-
llvm/test/MC/X86/apx/enqcmd-intel.s | 20 +++++++++
llvm/test/MC/X86/apx/keylocker-att.s | 21 ++++++++++
llvm/test/MC/X86/apx/keylocker-intel.s | 20 +++++++++
llvm/test/MC/X86/apx/user-msr-att.s | 41 +++++++++++++++++++
llvm/test/MC/X86/apx/user-msr-intel.s | 37 +++++++++++++++++
12 files changed, 295 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/user-msr.txt
create mode 100644 llvm/test/MC/X86/apx/user-msr-att.s
create mode 100644 llvm/test/MC/X86/apx/user-msr-intel.s
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index ce7f707066bb07e..5f8526136106645 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -941,6 +941,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
case VEX_LOB_MAP6:
insn->opcodeType = MAP6;
return consume(insn, insn->opcode);
+ case VEX_LOB_MAP7:
+ insn->opcodeType = MAP7;
+ return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index b1be4739617dfc7..166c796d3c5145a 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,7 +436,7 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-let Predicates = [HasUSERMSR], mayLoad = 1 in {
+let Predicates = [HasUSERMSR, NoEGPR], mayLoad = 1 in {
def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"urdmsr\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
@@ -444,7 +444,7 @@ let Predicates = [HasUSERMSR], mayLoad = 1 in {
"urdmsr\t{$imm, $dst|$dst, $imm}",
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
}
-let Predicates = [HasUSERMSR], mayStore = 1 in {
+let Predicates = [HasUSERMSR, NoEGPR], mayStore = 1 in {
def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"uwrmsr\t{$src2, $src1|$src1, $src2}",
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
@@ -452,6 +452,22 @@ let Predicates = [HasUSERMSR], mayStore = 1 in {
"uwrmsr\t{$src, $imm|$imm, $src}",
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
}
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
+ def URDMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T_MAP4, XD, EVEX, NoCD8;
+ def URDMSRri_EVEX : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}",
+ [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, EVEX, NoCD8;
+}
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayStore = 1 in {
+ def UWRMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T_MAP4, XS, EVEX, NoCD8;
+ def UWRMSRir_EVEX : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "uwrmsr\t{$src, $imm|$imm, $src}",
+ [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, EVEX, NoCD8;
+}
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index fa569affdd9ff3f..46bdfc81e9066c1 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -1,11 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr,+egpr | FileCheck %s --check-prefixes=EGPR
define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
; X64-LABEL: test_int_x86_urdmsr:
; X64: # %bb.0:
; X64-NEXT: urdmsr %rdi, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr:
+; EGPR: # %bb.0:
+; EGPR-NEXT: urdmsr %rdi, %rax # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0xc7]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 %A)
ret i64 %ret
}
@@ -15,6 +21,11 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
; X64: # %bb.0:
; X64-NEXT: urdmsr $123, %rax # encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr_const:
+; EGPR: # %bb.0:
+; EGPR-NEXT: urdmsr $123, %rax # encoding: [0x62,0xf7,0x7f,0x08,0xf8,0xc0,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 123)
ret i64 %ret
}
@@ -26,6 +37,13 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: urdmsr %rax, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_urdmsr_const_i64:
+; EGPR: # %bb.0:
+; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
+; EGPR-NEXT: # imm = 0x1FFFFFFFF
+; EGPR-NEXT: urdmsr %rax, %rax # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0xc0]
+; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 8589934591)
ret i64 %ret
}
@@ -37,6 +55,11 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr:
+; EGPR: # %bb.0:
+; EGPR-NEXT: uwrmsr %rsi, %rdi # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0xfe]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 %A, i64 %B)
ret void
}
@@ -46,6 +69,11 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rdi, $123 # encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr_const:
+; EGPR: # %bb.0:
+; EGPR-NEXT: uwrmsr %rdi, $123 # encoding: [0x62,0xf7,0x7e,0x08,0xf8,0xc7,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 123, i64 %A)
ret void
}
@@ -57,6 +85,13 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_uwrmsr_const_i64:
+; EGPR: # %bb.0:
+; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
+; EGPR-NEXT: # imm = 0x1FFFFFFFF
+; EGPR-NEXT: uwrmsr %rdi, %rax # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0xc7]
+; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 8589934591, i64 %A)
ret void
}
diff --git a/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
index 11e7a6cf0e10fbf..5b3dec4165dcb74 100644
--- a/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/enqcmd.txt
@@ -1,6 +1,8 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+## enqcmd
+
# ATT: enqcmd 123(%eax,%ebx,4), %ecx
# INTEL: enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b
@@ -16,3 +18,21 @@
# ATT: enqcmd 291(%r28,%r29,4), %r19
# INTEL: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
+
+## enqcmds
+
+# ATT: enqcmds 123(%eax,%ebx,4), %ecx
+# INTEL: enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmds 123(%rax,%rbx,4), %r9
+# INTEL: enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b
+
+# ATT: enqcmds 291(%r28d,%r29d,4), %r18d
+# INTEL: enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: enqcmds 291(%r28,%r29,4), %r19
+# INTEL: enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
index d74aa4886575dfb..c1ddef9ed4233de 100644
--- a/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/keylocker.txt
@@ -1,6 +1,8 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+## aesdec128kl
+
# ATT: aesdec128kl 123(%rax,%rbx,4), %xmm12
# INTEL: aesdec128kl xmm12, [rax + 4*rbx + 123]
0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b
@@ -9,6 +11,8 @@
# INTEL: aesdec128kl xmm12, [r28 + 4*r29 + 291]
0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
+## aesdec256kl
+
# ATT: aesdec256kl 123(%rax,%rbx,4), %xmm12
# INTEL: aesdec256kl xmm12, [rax + 4*rbx + 123]
0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b
@@ -17,6 +21,8 @@
# INTEL: aesdec256kl xmm12, [r28 + 4*r29 + 291]
0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00
+## aesdecwide128kl
+
# ATT: aesdecwide128kl 123(%rax,%rbx,4)
# INTEL: aesdecwide128kl [rax + 4*rbx + 123]
0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b
@@ -25,6 +31,8 @@
# INTEL: aesdecwide128kl [r28 + 4*r29 + 291]
0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00
+## aesdecwide256kl
+
# ATT: aesdecwide256kl 123(%rax,%rbx,4)
# INTEL: aesdecwide256kl [rax + 4*rbx + 123]
0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b
@@ -33,6 +41,8 @@
# INTEL: aesdecwide256kl [r28 + 4*r29 + 291]
0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00
+## aesenc128kl
+
# ATT: aesenc128kl 123(%rax,%rbx,4), %xmm12
# INTEL: aesenc128kl xmm12, [rax + 4*rbx + 123]
0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b
@@ -41,6 +51,8 @@
# INTEL: aesenc128kl xmm12, [r28 + 4*r29 + 291]
0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
+## aesenc256kl
+
# ATT: aesenc256kl 123(%rax,%rbx,4), %xmm12
# INTEL: aesenc256kl xmm12, [rax + 4*rbx + 123]
0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b
@@ -49,6 +61,8 @@
# INTEL: aesenc256kl xmm12, [r28 + 4*r29 + 291]
0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00
+## aesencwide128kl
+
# ATT: aesencwide128kl 123(%rax,%rbx,4)
# INTEL: aesencwide128kl [rax + 4*rbx + 123]
0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b
@@ -57,6 +71,8 @@
# INTEL: aesencwide128kl [r28 + 4*r29 + 291]
0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00
+## aesencwide256kl
+
# ATT: aesencwide256kl 123(%rax,%rbx,4)
# INTEL: aesencwide256kl [rax + 4*rbx + 123]
0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b
@@ -65,6 +81,8 @@
# INTEL: aesencwide256kl [r28 + 4*r29 + 291]
0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00
+## encodekey128
+
# ATT: encodekey128 %ecx, %edx
# INTEL: encodekey128 edx, ecx
0x62,0xf4,0x7e,0x08,0xda,0xd1
@@ -73,6 +91,8 @@
# INTEL: encodekey128 r22d, r18d
0x62,0xec,0x7e,0x08,0xda,0xf2
+## encodekey256
+
# ATT: encodekey256 %ecx, %edx
# INTEL: encodekey256 edx, ecx
0x62,0xf4,0x7e,0x08,0xdb,0xd1
diff --git a/llvm/test/MC/Disassembler/X86/apx/user-msr.txt b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
new file mode 100644
index 000000000000000..60cdab132485c61
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+## urdmsr
+
+# ATT: urdmsr $123, %r9
+# INTEL: urdmsr r9, 123
+0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r9, %r15
+# INTEL: urdmsr r15, r9
+0x62,0x54,0x7f,0x08,0xf8,0xf9
+
+# ATT: urdmsr $123, %r19
+# INTEL: urdmsr r19, 123
+0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r19, %r23
+# INTEL: urdmsr r23, r19
+0x62,0xec,0x7f,0x08,0xf8,0xfb
+
+## uwrmsr
+
+# ATT: uwrmsr %r9, $123
+# INTEL: uwrmsr 123, r9
+0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r9, %r15
+# INTEL: uwrmsr r15, r9
+0x62,0x54,0x7e,0x08,0xf8,0xf9
+
+# ATT: uwrmsr %r19, $123
+# INTEL: uwrmsr 123, r19
+0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r19, %r23
+# INTEL: uwrmsr r23, r19
+0x62,0xec,0x7e,0x08,0xf8,0xfb
diff --git a/llvm/test/MC/X86/apx/enqcmd-att.s b/llvm/test/MC/X86/apx/enqcmd-att.s
index 5716883edb18542..36975c512d10b12 100644
--- a/llvm/test/MC/X86/apx/enqcmd-att.s
+++ b/llvm/test/MC/X86/apx/enqcmd-att.s
@@ -1,8 +1,11 @@
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-# ERROR-COUNT-4: error:
+# ERROR-COUNT-8: error:
# ERROR-NOT: error:
+
+## enqcmd
+
# CHECK: {evex} enqcmd 123(%eax,%ebx,4), %ecx
# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
{evex} enqcmd 123(%eax,%ebx,4), %ecx
@@ -18,3 +21,21 @@
# CHECK: enqcmd 291(%r28,%r29,4), %r19
# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
enqcmd 291(%r28,%r29,4), %r19
+
+## enqcmds
+
+# CHECK: {evex} enqcmds 123(%eax,%ebx,4), %ecx
+# CHECK: encoding: [0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds 123(%eax,%ebx,4), %ecx
+
+# CHECK: {evex} enqcmds 123(%rax,%rbx,4), %r9
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds 123(%rax,%rbx,4), %r9
+
+# CHECK: enqcmds 291(%r28d,%r29d,4), %r18d
+# CHECK: encoding: [0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmds 291(%r28d,%r29d,4), %r18d
+
+# CHECK: enqcmds 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmds 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/enqcmd-intel.s b/llvm/test/MC/X86/apx/enqcmd-intel.s
index 3b176f11cd56d9c..8f4a48e9e6f6a16 100644
--- a/llvm/test/MC/X86/apx/enqcmd-intel.s
+++ b/llvm/test/MC/X86/apx/enqcmd-intel.s
@@ -1,5 +1,7 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+## enqcmd
+
# CHECK: {evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
# CHECK: encoding: [0x67,0x62,0xf4,0x7f,0x08,0xf8,0x4c,0x98,0x7b]
{evex} enqcmd ecx, zmmword ptr [eax + 4*ebx + 123]
@@ -15,3 +17,21 @@
# CHECK: enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x8c,0x7b,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
enqcmd r19, zmmword ptr [r28 + 4*r29 + 291]
+
+## enqcmds
+
+# CHECK: {evex} enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+# CHECK: encoding: [0x67,0x62,0xf4,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds ecx, zmmword ptr [eax + 4*ebx + 123]
+
+# CHECK: {evex} enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xf8,0x4c,0x98,0x7b]
+ {evex} enqcmds r9, zmmword ptr [rax + 4*rbx + 123]
+
+# CHECK: enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+# CHECK: encoding: [0x67,0x62,0x8c,0x7a,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ enqcmds r18d, zmmword ptr [r28d + 4*r29d + 291]
+
+# CHECK: enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x7a,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ enqcmds r19, zmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/keylocker-att.s b/llvm/test/MC/X86/apx/keylocker-att.s
index 101c26f4a0459aa..7c8db319df74a78 100644
--- a/llvm/test/MC/X86/apx/keylocker-att.s
+++ b/llvm/test/MC/X86/apx/keylocker-att.s
@@ -3,6 +3,9 @@
# ERROR-COUNT-20: error:
# ERROR-NOT: error:
+
+## aesdec128kl
+
# CHECK: {evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
{evex} aesdec128kl 123(%rax,%rbx,4), %xmm12
@@ -11,6 +14,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
aesdec128kl 291(%r28,%r29,4), %xmm12
+## aesdec256kl
+
# CHECK: {evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
{evex} aesdec256kl 123(%rax,%rbx,4), %xmm12
@@ -19,6 +24,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
aesdec256kl 291(%r28,%r29,4), %xmm12
+## aesdecwide128kl
+
# CHECK: {evex} aesdecwide128kl 123(%rax,%rbx,4)
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
{evex} aesdecwide128kl 123(%rax,%rbx,4)
@@ -27,6 +34,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
aesdecwide128kl 291(%r28,%r29,4)
+## aesdecwide256kl
+
# CHECK: {evex} aesdecwide256kl 123(%rax,%rbx,4)
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
{evex} aesdecwide256kl 123(%rax,%rbx,4)
@@ -35,6 +44,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
aesdecwide256kl 291(%r28,%r29,4)
+## aesenc128kl
+
# CHECK: {evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
{evex} aesenc128kl 123(%rax,%rbx,4), %xmm12
@@ -43,6 +54,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
aesenc128kl 291(%r28,%r29,4), %xmm12
+## aesenc256kl
+
# CHECK: {evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
{evex} aesenc256kl 123(%rax,%rbx,4), %xmm12
@@ -51,6 +64,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
aesenc256kl 291(%r28,%r29,4), %xmm12
+## aesencwide128kl
+
# CHECK: {evex} aesencwide128kl 123(%rax,%rbx,4)
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
{evex} aesencwide128kl 123(%rax,%rbx,4)
@@ -59,6 +74,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
aesencwide128kl 291(%r28,%r29,4)
+## aesencwide256kl
+
# CHECK: {evex} aesencwide256kl 123(%rax,%rbx,4)
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
{evex} aesencwide256kl 123(%rax,%rbx,4)
@@ -67,6 +84,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
aesencwide256kl 291(%r28,%r29,4)
+## encodekey128
+
# CHECK: {evex} encodekey128 %ecx, %edx
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
{evex} encodekey128 %ecx, %edx
@@ -75,6 +94,8 @@
# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
encodekey128 %r18d, %r22d
+## encodekey256
+
# CHECK: {evex} encodekey256 %ecx, %edx
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
{evex} encodekey256 %ecx, %edx
diff --git a/llvm/test/MC/X86/apx/keylocker-intel.s b/llvm/test/MC/X86/apx/keylocker-intel.s
index 92c93f43af0b994..b59fa001483d681 100644
--- a/llvm/test/MC/X86/apx/keylocker-intel.s
+++ b/llvm/test/MC/X86/apx/keylocker-intel.s
@@ -1,5 +1,7 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+## aesdec128kl
+
# CHECK: {evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdd,0x64,0x98,0x7b]
{evex} aesdec128kl xmm12, [rax + 4*rbx + 123]
@@ -8,6 +10,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
aesdec128kl xmm12, [r28 + 4*r29 + 291]
+## aesdec256kl
+
# CHECK: {evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdf,0x64,0x98,0x7b]
{evex} aesdec256kl xmm12, [rax + 4*rbx + 123]
@@ -16,6 +20,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdf,0xa4,0xac,0x23,0x01,0x00,0x00]
aesdec256kl xmm12, [r28 + 4*r29 + 291]
+## aesdecwide128kl
+
# CHECK: {evex} aesdecwide128kl [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x4c,0x98,0x7b]
{evex} aesdecwide128kl [rax + 4*rbx + 123]
@@ -24,6 +30,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x8c,0xac,0x23,0x01,0x00,0x00]
aesdecwide128kl [r28 + 4*r29 + 291]
+## aesdecwide256kl
+
# CHECK: {evex} aesdecwide256kl [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x5c,0x98,0x7b]
{evex} aesdecwide256kl [rax + 4*rbx + 123]
@@ -32,6 +40,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x9c,0xac,0x23,0x01,0x00,0x00]
aesdecwide256kl [r28 + 4*r29 + 291]
+## aesenc128kl
+
# CHECK: {evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xdc,0x64,0x98,0x7b]
{evex} aesenc128kl xmm12, [rax + 4*rbx + 123]
@@ -40,6 +50,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
aesenc128kl xmm12, [r28 + 4*r29 + 291]
+## aesenc256kl
+
# CHECK: {evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0x74,0x7e,0x08,0xde,0x64,0x98,0x7b]
{evex} aesenc256kl xmm12, [rax + 4*rbx + 123]
@@ -48,6 +60,8 @@
# CHECK: encoding: [0x62,0x1c,0x7a,0x08,0xde,0xa4,0xac,0x23,0x01,0x00,0x00]
aesenc256kl xmm12, [r28 + 4*r29 + 291]
+## aesencwide128kl
+
# CHECK: {evex} aesencwide128kl [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x44,0x98,0x7b]
{evex} aesencwide128kl [rax + 4*rbx + 123]
@@ -56,6 +70,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x84,0xac,0x23,0x01,0x00,0x00]
aesencwide128kl [r28 + 4*r29 + 291]
+## aesencwide256kl
+
# CHECK: {evex} aesencwide256kl [rax + 4*rbx + 123]
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x54,0x98,0x7b]
{evex} aesencwide256kl [rax + 4*rbx + 123]
@@ -64,6 +80,8 @@
# CHECK: encoding: [0x62,0x9c,0x7a,0x08,0xd8,0x94,0xac,0x23,0x01,0x00,0x00]
aesencwide256kl [r28 + 4*r29 + 291]
+## encodekey128
+
# CHECK: {evex} encodekey128 edx, ecx
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xda,0xd1]
{evex} encodekey128 edx, ecx
@@ -72,6 +90,8 @@
# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xda,0xf2]
encodekey128 r22d, r18d
+## encodekey256
+
# CHECK: {evex} encodekey256 edx, ecx
# CHECK: encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xd1]
{evex} encodekey256 edx, ecx
diff --git a/llvm/test/MC/X86/apx/user-msr-att.s b/llvm/test/MC/X86/apx/user-msr-att.s
new file mode 100644
index 000000000000000..59df5895d53ec1d
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-att.s
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-8: error:
+# ERROR-NOT: error:
+
+## urdmsr
+
+# CHECK: {evex} urdmsr $123, %r9
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr $123, %r9
+
+# CHECK: {evex} urdmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr %r9, %r15
+
+# CHECK: urdmsr $123, %r19
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr $123, %r19
+
+# CHECK: urdmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr %r19, %r23
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr %r9, $123
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr %r9, $123
+
+# CHECK: {evex} uwrmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr %r9, %r15
+
+# CHECK: uwrmsr %r19, $123
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr %r19, $123
+
+# CHECK: uwrmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr %r19, %r23
diff --git a/llvm/test/MC/X86/apx/user-msr-intel.s b/llvm/test/MC/X86/apx/user-msr-intel.s
new file mode 100644
index 000000000000000..b6f43e85834c084
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-intel.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## urdmsr
+
+# CHECK: {evex} urdmsr r9, 123
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr r9, 123
+
+# CHECK: {evex} urdmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr r15, r9
+
+# CHECK: urdmsr r19, 123
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr r19, 123
+
+# CHECK: urdmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr r23, r19
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr 123, r9
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr 123, r9
+
+# CHECK: {evex} uwrmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr r15, r9
+
+# CHECK: uwrmsr 123, r19
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr 123, r19
+
+# CHECK: uwrmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr r23, r19
>From e446e52af8b98300e2816424a6505537e1695350 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 8 Jan 2024 17:41:42 -0800
Subject: [PATCH 03/13] resolve comments
---
llvm/test/CodeGen/X86/enqcmd-intrinsics.ll | 4 ++--
.../X86/keylocker-intrinsics-fast-isel.ll | 20 +++++++++----------
llvm/test/CodeGen/X86/usermsr-intrinsics.ll | 12 +++++------
llvm/utils/TableGen/X86RecognizableInstr.cpp | 5 -----
4 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
index 230a2ffc059413a..0b09c8fc1e74e65 100644
--- a/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/enqcmd-intrinsics.ll
@@ -27,7 +27,7 @@ define i8 @test_enqcmd(ptr %dst, ptr %src) {
;
; EGPR-LABEL: test_enqcmd:
; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: enqcmd (%rsi), %rdi # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0x3e]
+; EGPR-NEXT: enqcmd (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0x3e]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
@@ -60,7 +60,7 @@ define i8 @test_enqcmds(ptr %dst, ptr %src) {
;
; EGPR-LABEL: test_enqcmds:
; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: enqcmds (%rsi), %rdi # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0x3e]
+; EGPR-NEXT: enqcmds (%rsi), %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0x3e]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: retq # encoding: [0xc3]
entry:
diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
index 1d90d1c31d5ca89..ae046be9a508326 100644
--- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
+++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
@@ -35,7 +35,7 @@ define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, ptr nocapture %h)
;
; EGPR-LABEL: test_encodekey128_u32:
; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: encodekey128 %edi, %eax # encoding: [0x62,0xf4,0x7e,0x08,0xda,0xc7]
+; EGPR-NEXT: encodekey128 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfa,0xc7]
; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
@@ -81,7 +81,7 @@ define i32 @test_encodekey256_u32(i32 %htype, <2 x i64> %key_lo, <2 x i64> %key_
;
; EGPR-LABEL: test_encodekey256_u32:
; EGPR: # %bb.0: # %entry
-; EGPR-NEXT: encodekey256 %edi, %eax # encoding: [0x62,0xf4,0x7e,0x08,0xdb,0xc7]
+; EGPR-NEXT: encodekey256 %edi, %eax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfb,0xc7]
; EGPR-NEXT: movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
; EGPR-NEXT: movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
; EGPR-NEXT: movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
@@ -128,7 +128,7 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; EGPR-LABEL: test_mm_aesenc256kl_u8:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xde,0x06]
+; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xde,0x06]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
@@ -152,7 +152,7 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; EGPR-LABEL: test_mm_aesdec256kl_u8:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdf,0x06]
+; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdf,0x06]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
@@ -176,7 +176,7 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; EGPR-LABEL: test_mm_aesenc128kl_u8:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdc,0x06]
+; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdc,0x06]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
@@ -200,7 +200,7 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h)
; EGPR-LABEL: test_mm_aesdec128kl_u8:
; EGPR: # %bb.0: # %entry
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # encoding: [0x62,0xf4,0x7e,0x08,0xdd,0x06]
+; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdd,0x06]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: retq # encoding: [0xc3]
@@ -247,7 +247,7 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesencwide128kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x02]
+; EGPR-NEXT: aesencwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x02]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
@@ -337,7 +337,7 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) {
; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesdecwide128kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x0a]
+; EGPR-NEXT: aesdecwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x0a]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
@@ -427,7 +427,7 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesencwide256kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x12]
+; EGPR-NEXT: aesencwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x12]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
@@ -517,7 +517,7 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) {
; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60]
; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70]
; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; EGPR-NEXT: aesdecwide256kl (%rdx) # encoding: [0x62,0xf4,0x7e,0x08,0xd8,0x1a]
+; EGPR-NEXT: aesdecwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x1a]
; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07]
; EGPR-NEXT: movaps %xmm1, 16(%rdi) # encoding: [0x0f,0x29,0x4f,0x10]
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index 46bdfc81e9066c1..42fe8d4f3f7d841 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -10,7 +10,7 @@ define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
;
; EGPR-LABEL: test_int_x86_urdmsr:
; EGPR: # %bb.0:
-; EGPR-NEXT: urdmsr %rdi, %rax # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0xc7]
+; EGPR-NEXT: urdmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 %A)
ret i64 %ret
@@ -24,7 +24,7 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
;
; EGPR-LABEL: test_int_x86_urdmsr_const:
; EGPR: # %bb.0:
-; EGPR-NEXT: urdmsr $123, %rax # encoding: [0x62,0xf7,0x7f,0x08,0xf8,0xc0,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: urdmsr $123, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 123)
ret i64 %ret
@@ -42,7 +42,7 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
; EGPR-NEXT: # imm = 0x1FFFFFFFF
-; EGPR-NEXT: urdmsr %rax, %rax # encoding: [0x62,0xf4,0x7f,0x08,0xf8,0xc0]
+; EGPR-NEXT: urdmsr %rax, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
; EGPR-NEXT: retq # encoding: [0xc3]
%ret = call i64 @llvm.x86.urdmsr(i64 8589934591)
ret i64 %ret
@@ -58,7 +58,7 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
;
; EGPR-LABEL: test_int_x86_uwrmsr:
; EGPR: # %bb.0:
-; EGPR-NEXT: uwrmsr %rsi, %rdi # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0xfe]
+; EGPR-NEXT: uwrmsr %rsi, %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 %A, i64 %B)
ret void
@@ -72,7 +72,7 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
;
; EGPR-LABEL: test_int_x86_uwrmsr_const:
; EGPR: # %bb.0:
-; EGPR-NEXT: uwrmsr %rdi, $123 # encoding: [0x62,0xf7,0x7e,0x08,0xf8,0xc7,0x7b,0x00,0x00,0x00]
+; EGPR-NEXT: uwrmsr %rdi, $123 # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 123, i64 %A)
ret void
@@ -90,7 +90,7 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
; EGPR-NEXT: # imm = 0x1FFFFFFFF
-; EGPR-NEXT: uwrmsr %rdi, %rax # encoding: [0x62,0xf4,0x7e,0x08,0xf8,0xc7]
+; EGPR-NEXT: uwrmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; EGPR-NEXT: retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 8589934591, i64 %A)
ret void
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index c2032e576dd087e..18f961065c23320 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -168,11 +168,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
void RecognizableInstr::processInstr(DisassemblerTables &tables,
const CodeGenInstruction &insn,
InstrUID uid) {
- if (insn.TheDef->getName() == "ENQCMD32_EVEX")
- {
- if (insn.TheDef->getName() == "yikarus")
- return;
- }
if (!insn.TheDef->isSubClassOf("X86Inst"))
return;
RecognizableInstr recogInstr(tables, insn, uid);
>From a0968a5ac84ba14ec75bc41d743bdb1cfcc984a0 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Mon, 8 Jan 2024 17:53:23 -0800
Subject: [PATCH 04/13] clang format
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 679382fcf438c93..42923192f79d788 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5036,8 +5036,12 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
- case Intrinsic::x86_encodekey128: Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128); break;
- case Intrinsic::x86_encodekey256: Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256); break;
+ case Intrinsic::x86_encodekey128:
+ Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
+ break;
+ case Intrinsic::x86_encodekey256:
+ Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256);
+ break;
#undef GET_EGPR_IF_ENABLED
}
>From c2f50fc1c8c07e2bbb589625ea9a785287b67034 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Tue, 9 Jan 2024 18:05:30 -0800
Subject: [PATCH 05/13] add braces to macro
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 42923192f79d788..892c3c6732e514c 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5035,7 +5035,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
-#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
+#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC)
case Intrinsic::x86_encodekey128:
Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
break;
@@ -6399,7 +6399,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
switch (Node->getOpcode()) {
default:
llvm_unreachable("Unexpected opcode!");
-#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
+#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC)
case X86ISD::AESENCWIDE128KL:
Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
break;
>From bf8421ecc1720203d53c83f8dfd7455ffa9d60f9 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 10 Jan 2024 01:17:37 -0800
Subject: [PATCH 06/13] remove redundant define
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 892c3c6732e514c..d77306b32dc33a1 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5042,7 +5042,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
case Intrinsic::x86_encodekey256:
Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY256);
break;
-#undef GET_EGPR_IF_ENABLED
}
SDValue Chain = Node->getOperand(0);
@@ -6399,7 +6398,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
switch (Node->getOpcode()) {
default:
llvm_unreachable("Unexpected opcode!");
-#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC)
case X86ISD::AESENCWIDE128KL:
Opcode = GET_EGPR_IF_ENABLED(X86::AESENCWIDE128KL);
break;
>From 9794951384a5b52ad70d3e188aa9fd807e5cc16f Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Fri, 19 Jan 2024 00:49:30 -0800
Subject: [PATCH 07/13] adjust intent and rebase
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 -
llvm/lib/Target/X86/X86InstrKL.td | 85 +++++++++++--------------
2 files changed, 37 insertions(+), 50 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index d77306b32dc33a1..c0b7a5523b5d8f3 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5035,7 +5035,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode;
switch (IntNo) {
default: llvm_unreachable("Impossible intrinsic");
-#define GET_EGPR_IF_ENABLED(OPC) (Subtarget->hasEGPR() ? OPC##_EVEX : OPC)
case Intrinsic::x86_encodekey128:
Opcode = GET_EGPR_IF_ENABLED(X86::ENCODEKEY128);
break;
@@ -5519,7 +5518,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
LoReg = UseMULX ? X86::RDX : X86::RAX;
HiReg = X86::RDX;
break;
-#undef GET_EGPR_IF_ENABLED
}
SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 5dfd5e7493128bd..a68f749c8513de8 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -31,43 +31,33 @@ let SchedRW = [WriteSystem] in {
}
let Predicates = [HasKL, NoEGPR] in {
- let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
- }
-
- let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
- }
-
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in {
- def AESENC128KL : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, T8;
-
- def AESDEC128KL : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, T8;
-
- def AESENC256KL : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, T8;
-
- def AESDEC256KL : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, T8;
- }
+ let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY128 : Encodekey<0xFA, "encodekey128">, T8;
+
+ let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
+
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in {
+ def AESENC128KL : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, T8;
+ def AESDEC128KL : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, T8;
+ def AESENC256KL : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, T8;
+ def AESDEC256KL : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, T8;
+ }
}
let Predicates = [HasKL, HasEGPR, In64BitMode] in {
- let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
- }
-
- let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
- def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
- }
-
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
- def AESENC128KL_EVEX : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, EVEX, T_MAP4;
-
- def AESDEC128KL_EVEX : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, EVEX, T_MAP4;
-
- def AESENC256KL_EVEX : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, EVEX, T_MAP4;
-
- def AESDEC256KL_EVEX : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, EVEX, T_MAP4;
- }
+ let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY128_EVEX : Encodekey<0xDA, "encodekey128">, EVEX, T_MAP4;
+
+ let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
+ def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
+
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
+ def AESENC128KL_EVEX : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, EVEX, T_MAP4;
+ def AESDEC128KL_EVEX : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, EVEX, T_MAP4;
+ def AESENC256KL_EVEX : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, EVEX, T_MAP4;
+ def AESDEC256KL_EVEX : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, EVEX, T_MAP4;
+ }
}
} // SchedRW
@@ -78,19 +68,18 @@ let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
mayLoad = 1 in {
- let Predicates = [HasWIDEKL, NoEGPR] in {
- def AESENCWIDE128KL : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, T8;
- def AESDECWIDE128KL : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, T8;
- def AESENCWIDE256KL : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, T8;
- def AESDECWIDE256KL : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, T8;
- }
-
- let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in {
- def AESENCWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, EVEX, T_MAP4;
- def AESDECWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, EVEX, T_MAP4;
- def AESENCWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, EVEX, T_MAP4;
- def AESDECWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, EVEX, T_MAP4;
+ let Predicates = [HasWIDEKL, NoEGPR] in {
+ def AESENCWIDE128KL : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, T8;
+ def AESDECWIDE128KL : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, T8;
+ def AESENCWIDE256KL : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, T8;
+ def AESDECWIDE256KL : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, T8;
+ }
+
+ let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in {
+ def AESENCWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, EVEX, T_MAP4;
+ def AESDECWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, EVEX, T_MAP4;
+ def AESENCWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, EVEX, T_MAP4;
+ def AESDECWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, EVEX, T_MAP4;
+ }
}
- }
-
} // SchedRW, Predicates
>From 46d0cffc72165980266f0313f12f17bb13c8bfe7 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Tue, 23 Jan 2024 23:24:00 -0800
Subject: [PATCH 08/13] use multiclass
---
llvm/lib/Target/X86/X86InstrKL.td | 72 +++++++++++++++------------
llvm/lib/Target/X86/X86InstrMisc.td | 72 +++++++++++----------------
llvm/lib/Target/X86/X86InstrSystem.td | 57 ++++++++++-----------
3 files changed, 98 insertions(+), 103 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index a68f749c8513de8..751a813ed6b2b07 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -14,14 +14,32 @@
//===----------------------------------------------------------------------===//
// Key Locker instructions
-class Encodekey<bits<8> opcode, string mnemonic>
- : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), mnemonic#"\t{$src, $dst|$dst, $src}", []>,
+class Encodekey<bits<8> opcode, string m>
+ : I<opcode, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), m#"\t{$src, $dst|$dst, $src}", []>,
NoCD8, XS;
-class Aesencdec<bits<8> opcode, string mnemonic, SDNode node>
- : I<opcode, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
- mnemonic#"\t{$src2, $src1|$src1, $src2}",
- [(set VR128:$dst, EFLAGS, (node VR128:$src1, addr:$src2))]>, NoCD8, XS;
+multiclass Aesencdec<string suffix> {
+ def AESENC128KL#suffix : I<0xDC, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesenc128kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESDEC128KL#suffix : I<0xDD, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesdec128kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESENC256KL#suffix : I<0xDE, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesenc256kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+ def AESDEC256KL#suffix : I<0xDF, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, opaquemem:$src2),
+ "aesdec256kl\t{$src2, $src1|$src1, $src2}",
+ [(set VR128:$dst, EFLAGS, (X86aesdec256kl VR128:$src1, addr:$src2))]>,
+ NoCD8, XS;
+}
let SchedRW = [WriteSystem] in {
let Uses = [XMM0, EAX], Defs = [EFLAGS], Predicates = [HasKL] in {
@@ -37,12 +55,8 @@ let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in {
- def AESENC128KL : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, T8;
- def AESDEC128KL : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, T8;
- def AESENC256KL : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, T8;
- def AESDEC256KL : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, T8;
- }
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in
+ defm "" : Aesencdec<"">, T8;
}
let Predicates = [HasKL, HasEGPR, In64BitMode] in {
@@ -52,34 +66,26 @@ let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
- def AESENC128KL_EVEX : Aesencdec<0xDC, "aesenc128kl", X86aesenc128kl>, EVEX, T_MAP4;
- def AESDEC128KL_EVEX : Aesencdec<0xDD, "aesdec128kl", X86aesdec128kl>, EVEX, T_MAP4;
- def AESENC256KL_EVEX : Aesencdec<0xDE, "aesenc256kl", X86aesenc256kl>, EVEX, T_MAP4;
- def AESDEC256KL_EVEX : Aesencdec<0xDF, "aesdec256kl", X86aesdec256kl>, EVEX, T_MAP4;
- }
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in
+ defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
}
} // SchedRW
-class Aesencdecwide<bits<8> opcode, Format f, string mnemonic>
- : I<opcode, f, (outs), (ins opaquemem:$src), mnemonic#"\t$src", []>, NoCD8, XS;
+multiclass Aesencdecwide<string suffix> {
+ def AESENCWIDE128KL#suffix : I<0xD8, MRM0m, (outs), (ins opaquemem:$src), "aesencwide128kl\t$src", []>, NoCD8, XS;
+ def AESDECWIDE128KL#suffix : I<0xD8, MRM1m, (outs), (ins opaquemem:$src), "aesdecwide128kl\t$src", []>, NoCD8, XS;
+ def AESENCWIDE256KL#suffix : I<0xD8, MRM2m, (outs), (ins opaquemem:$src), "aesencwide256kl\t$src", []>, NoCD8, XS;
+ def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
+}
let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
mayLoad = 1 in {
- let Predicates = [HasWIDEKL, NoEGPR] in {
- def AESENCWIDE128KL : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, T8;
- def AESDECWIDE128KL : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, T8;
- def AESENCWIDE256KL : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, T8;
- def AESDECWIDE256KL : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, T8;
- }
+ let Predicates = [HasWIDEKL, NoEGPR] in
+ defm "" : Aesencdecwide<"">, T8;
- let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in {
- def AESENCWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM0m, "aesencwide128kl">, EVEX, T_MAP4;
- def AESDECWIDE128KL_EVEX : Aesencdecwide<0xD8, MRM1m, "aesdecwide128kl">, EVEX, T_MAP4;
- def AESENCWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM2m, "aesencwide256kl">, EVEX, T_MAP4;
- def AESDECWIDE256KL_EVEX : Aesencdecwide<0xD8, MRM3m, "aesdecwide256kl">, EVEX, T_MAP4;
- }
+ let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
+ defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
}
-} // SchedRW, Predicates
+} // SchedRW
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 250325577c7af5a..f533cee2c437252 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1557,52 +1557,40 @@ def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$
//===----------------------------------------------------------------------===//
// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
//
+multiclass Enqcmds<string suffix> {
+ def ENQCMD32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
+ NoCD8, XD, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
+ def ENQCMD64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
+ NoCD8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
+
+ def ENQCMDS32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
+ NoCD8, XS, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
+ def ENQCMDS64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
+ NoCD8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
+}
+
let SchedRW = [WriteStore], Defs = [EFLAGS] in {
def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
T8, XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
- def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
- T8, XD, AdSize32, Requires<[HasENQCMD]>;
- def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
- T8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
-
def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
- T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
- def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
- T8, XS, AdSize32, Requires<[HasENQCMD]>;
- def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
- T8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
-
-let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in {
- def ENQCMD32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
- EVEX, NoCD8, T_MAP4, XD, AdSize32;
- def ENQCMD64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmd\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
- EVEX, NoCD8, T_MAP4, XD, AdSize64;
-
- def ENQCMDS32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
- EVEX, NoCD8, T_MAP4, XS, AdSize32;
- def ENQCMDS64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
- "enqcmds\t{$src, $dst|$dst, $src}",
- [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
- EVEX, NoCD8, T_MAP4, XS, AdSize64;
-}
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
+ T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
+
+ defm "" : Enqcmds<"">, T8;
+ let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in
+ defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4;
+
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 166c796d3c5145a..74e99c7b090c878 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,37 +436,38 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-let Predicates = [HasUSERMSR, NoEGPR], mayLoad = 1 in {
- def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "urdmsr\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
- def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
- "urdmsr\t{$imm, $dst|$dst, $imm}",
- [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
+multiclass Urdwrmsr_rr<string suffix> {
+ let mayLoad = 1 in
+ def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
+ let mayStore = 1 in
+ def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
}
-let Predicates = [HasUSERMSR, NoEGPR], mayStore = 1 in {
- def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
- def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
- "uwrmsr\t{$src, $imm|$imm, $src}",
- [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
+
+multiclass Urdwrmsr_ri<string suffix> {
+ let mayLoad = 1 in
+ def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}",
+ [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
+ T_MAP7, XD, NoCD8;
+ let mayStore = 1 in
+ def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "uwrmsr\t{$src, $imm|$imm, $src}",
+ [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
+ T_MAP7, XS, NoCD8;
}
-let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
- def URDMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "urdmsr\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T_MAP4, XD, EVEX, NoCD8;
- def URDMSRri_EVEX : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
- "urdmsr\t{$imm, $dst|$dst, $imm}",
- [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, EVEX, NoCD8;
+
+let Predicates = [HasUSERMSR, NoEGPR] in {
+ defm "" : Urdwrmsr_rr<"">, T8;
+ defm "" : Urdwrmsr_ri<"">, VEX;
}
-let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayStore = 1 in {
- def UWRMSRrr_EVEX : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T_MAP4, XS, EVEX, NoCD8;
- def UWRMSRir_EVEX : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
- "uwrmsr\t{$src, $imm|$imm, $src}",
- [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, EVEX, NoCD8;
+
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
+ defm "" : Urdwrmsr_rr<"_EVEX">, EVEX, T_MAP4;
+ defm "" : Urdwrmsr_ri<"_EVEX">, EVEX;
}
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
>From 1f592119f4454933f84ad8f2e868141ef229cb2e Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 24 Jan 2024 01:45:46 -0800
Subject: [PATCH 09/13] resolve comments
---
llvm/lib/Target/X86/X86InstrKL.td | 15 +++++------
llvm/lib/Target/X86/X86InstrMisc.td | 13 +++++----
llvm/lib/Target/X86/X86InstrSystem.td | 38 ++++++++++++---------------
3 files changed, 29 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 751a813ed6b2b07..71f71b4294d7385 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -78,14 +78,11 @@ multiclass Aesencdecwide<string suffix> {
def AESDECWIDE256KL#suffix : I<0xD8, MRM3m, (outs), (ins opaquemem:$src), "aesdecwide256kl\t$src", []>, NoCD8, XS;
}
-let SchedRW = [WriteSystem] in {
- let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
- Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
- mayLoad = 1 in {
- let Predicates = [HasWIDEKL, NoEGPR] in
- defm "" : Aesencdecwide<"">, T8;
+let SchedRW = [WriteSystem], Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
+ Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7], mayLoad = 1 in {
+ let Predicates = [HasWIDEKL, NoEGPR] in
+ defm "" : Aesencdecwide<"">, T8;
- let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
- defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
- }
+ let Predicates = [HasWIDEKL, HasEGPR, In64BitMode] in
+ defm "" : Aesencdecwide<"_EVEX">, EVEX, T_MAP4;
} // SchedRW
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index f533cee2c437252..c8e8d3f3ed58004 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1561,20 +1561,20 @@ multiclass Enqcmds<string suffix> {
def ENQCMD32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
"enqcmd\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
- NoCD8, XD, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
+ NoCD8, XD, AdSize32;
def ENQCMD64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
"enqcmd\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
- NoCD8, XD, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
+ NoCD8, XD, AdSize64;
def ENQCMDS32#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
"enqcmds\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
- NoCD8, XS, AdSize32, Requires<[HasENQCMD, NoEGPR]>;
+ NoCD8, XS, AdSize32;
def ENQCMDS64#suffix : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
"enqcmds\t{$src, $dst|$dst, $src}",
[(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
- NoCD8, XS, AdSize64, Requires<[HasENQCMD, NoEGPR, In64BitMode]>;
+ NoCD8, XS, AdSize64;
}
let SchedRW = [WriteStore], Defs = [EFLAGS] in {
@@ -1587,9 +1587,8 @@ let SchedRW = [WriteStore], Defs = [EFLAGS] in {
[(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
T8, XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
- defm "" : Enqcmds<"">, T8;
- let Predicates = [HasENQCMD, HasEGPR, In64BitMode] in
- defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4;
+ defm "" : Enqcmds<"">, T8, Requires<[HasENQCMD, NoEGPR]>;
+ defm "" : Enqcmds<"_EVEX">, EVEX, T_MAP4, Requires<[HasENQCMD, HasEGPR, In64BitMode]>;
}
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 74e99c7b090c878..a7899a2492b8823 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,39 +436,35 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-multiclass Urdwrmsr_rr<string suffix> {
- let mayLoad = 1 in
+multiclass Urdwrmsr<Map rrmap, string suffix> {
+ let mayLoad = 1 in {
+ let OpMap = rrmap in
def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"urdmsr\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
- let mayStore = 1 in
- def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
-}
-
-multiclass Urdwrmsr_ri<string suffix> {
- let mayLoad = 1 in
def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
"urdmsr\t{$imm, $dst|$dst, $imm}",
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
- T_MAP7, XD, NoCD8;
- let mayStore = 1 in
+ T_MAP7, VEX, XD, NoCD8;
+}
+ let mayStore = 1 in {
+ let OpMap = rrmap in
+ def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
"uwrmsr\t{$src, $imm|$imm, $src}",
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
- T_MAP7, XS, NoCD8;
+ T_MAP7, VEX, XS, NoCD8;
+ }
}
-let Predicates = [HasUSERMSR, NoEGPR] in {
- defm "" : Urdwrmsr_rr<"">, T8;
- defm "" : Urdwrmsr_ri<"">, VEX;
-}
+let Predicates = [HasUSERMSR, NoEGPR] in
+ defm "" : Urdwrmsr<T8, "">;
+
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
+ defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
-let Predicates = [HasUSERMSR, HasEGPR, In64BitMode], mayLoad = 1 in {
- defm "" : Urdwrmsr_rr<"_EVEX">, EVEX, T_MAP4;
- defm "" : Urdwrmsr_ri<"_EVEX">, EVEX;
-}
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
>From 9eb329640cdb5c3573a3875b5060a932f00d748d Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 24 Jan 2024 02:12:24 -0800
Subject: [PATCH 10/13] resolve comment
---
llvm/lib/Target/X86/X86InstrKL.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrKL.td b/llvm/lib/Target/X86/X86InstrKL.td
index 71f71b4294d7385..32423e08ed4c53a 100644
--- a/llvm/lib/Target/X86/X86InstrKL.td
+++ b/llvm/lib/Target/X86/X86InstrKL.td
@@ -55,7 +55,7 @@ let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
def ENCODEKEY256 : Encodekey<0xFB, "encodekey256">, T8;
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [NoEGPR] in
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
defm "" : Aesencdec<"">, T8;
}
@@ -66,7 +66,7 @@ let SchedRW = [WriteSystem] in {
let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in
def ENCODEKEY256_EVEX : Encodekey<0xDB, "encodekey256">, EVEX, T_MAP4;
- let Constraints = "$src1 = $dst", Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in
+ let Constraints = "$src1 = $dst", Defs = [EFLAGS] in
defm "" : Aesencdec<"_EVEX">, EVEX, T_MAP4;
}
} // SchedRW
>From 7f09d85e90bf868f098019c99716e30ea76f04de Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 24 Jan 2024 18:41:03 -0800
Subject: [PATCH 11/13] resolve
---
.../Support/X86DisassemblerDecoderCommon.h | 2 -
.../X86/Disassembler/X86Disassembler.cpp | 3 --
llvm/lib/Target/X86/X86InstrSystem.td | 41 +++++++------------
.../test/MC/Disassembler/X86/apx/user-msr.txt | 38 -----------------
llvm/test/MC/X86/apx/user-msr-att.s | 41 -------------------
llvm/test/MC/X86/apx/user-msr-intel.s | 37 -----------------
llvm/utils/TableGen/X86DisassemblerTables.cpp | 8 +---
llvm/utils/TableGen/X86RecognizableInstr.cpp | 10 +++--
8 files changed, 21 insertions(+), 159 deletions(-)
delete mode 100644 llvm/test/MC/Disassembler/X86/apx/user-msr.txt
delete mode 100644 llvm/test/MC/X86/apx/user-msr-att.s
delete mode 100644 llvm/test/MC/X86/apx/user-msr-intel.s
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 0dc974ea9efd8d1..3aceb247a26c21e 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -140,9 +140,7 @@ enum attributeBits {
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
- ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
- ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 5f8526136106645..ce7f707066bb07e 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -941,9 +941,6 @@ static bool readOpcode(struct InternalInstruction *insn) {
case VEX_LOB_MAP6:
insn->opcodeType = MAP6;
return consume(insn, insn->opcode);
- case VEX_LOB_MAP7:
- insn->opcodeType = MAP7;
- return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index a7899a2492b8823..74b478212f17487 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,34 +436,21 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-multiclass Urdwrmsr<Map rrmap, string suffix> {
- let mayLoad = 1 in {
- let OpMap = rrmap in
- def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "urdmsr\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
- def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
- "urdmsr\t{$imm, $dst|$dst, $imm}",
- [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
- T_MAP7, VEX, XD, NoCD8;
+let Predicates = [HasUSERMSR], mayLoad = 1 in {
+ def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
+ def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}",
+ [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
}
- let mayStore = 1 in {
- let OpMap = rrmap in
- def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
- def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
- "uwrmsr\t{$src, $imm|$imm, $src}",
- [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
- T_MAP7, VEX, XS, NoCD8;
- }
-}
-
-let Predicates = [HasUSERMSR, NoEGPR] in
- defm "" : Urdwrmsr<T8, "">;
-
-let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
- defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
+let Predicates = [HasUSERMSR], mayStore = 1 in {
+ def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
+ def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "uwrmsr\t{$src, $imm|$imm, $src}",
+ [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
diff --git a/llvm/test/MC/Disassembler/X86/apx/user-msr.txt b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
deleted file mode 100644
index 60cdab132485c61..000000000000000
--- a/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
-# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-
-## urdmsr
-
-# ATT: urdmsr $123, %r9
-# INTEL: urdmsr r9, 123
-0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
-
-# ATT: urdmsr %r9, %r15
-# INTEL: urdmsr r15, r9
-0x62,0x54,0x7f,0x08,0xf8,0xf9
-
-# ATT: urdmsr $123, %r19
-# INTEL: urdmsr r19, 123
-0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
-
-# ATT: urdmsr %r19, %r23
-# INTEL: urdmsr r23, r19
-0x62,0xec,0x7f,0x08,0xf8,0xfb
-
-## uwrmsr
-
-# ATT: uwrmsr %r9, $123
-# INTEL: uwrmsr 123, r9
-0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
-
-# ATT: uwrmsr %r9, %r15
-# INTEL: uwrmsr r15, r9
-0x62,0x54,0x7e,0x08,0xf8,0xf9
-
-# ATT: uwrmsr %r19, $123
-# INTEL: uwrmsr 123, r19
-0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
-
-# ATT: uwrmsr %r19, %r23
-# INTEL: uwrmsr r23, r19
-0x62,0xec,0x7e,0x08,0xf8,0xfb
diff --git a/llvm/test/MC/X86/apx/user-msr-att.s b/llvm/test/MC/X86/apx/user-msr-att.s
deleted file mode 100644
index 59df5895d53ec1d..000000000000000
--- a/llvm/test/MC/X86/apx/user-msr-att.s
+++ /dev/null
@@ -1,41 +0,0 @@
-# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
-# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-
-# ERROR-COUNT-8: error:
-# ERROR-NOT: error:
-
-## urdmsr
-
-# CHECK: {evex} urdmsr $123, %r9
-# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
- {evex} urdmsr $123, %r9
-
-# CHECK: {evex} urdmsr %r9, %r15
-# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
- {evex} urdmsr %r9, %r15
-
-# CHECK: urdmsr $123, %r19
-# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
- urdmsr $123, %r19
-
-# CHECK: urdmsr %r19, %r23
-# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
- urdmsr %r19, %r23
-
-## uwrmsr
-
-# CHECK: {evex} uwrmsr %r9, $123
-# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
- {evex} uwrmsr %r9, $123
-
-# CHECK: {evex} uwrmsr %r9, %r15
-# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
- {evex} uwrmsr %r9, %r15
-
-# CHECK: uwrmsr %r19, $123
-# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
- uwrmsr %r19, $123
-
-# CHECK: uwrmsr %r19, %r23
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
- uwrmsr %r19, %r23
diff --git a/llvm/test/MC/X86/apx/user-msr-intel.s b/llvm/test/MC/X86/apx/user-msr-intel.s
deleted file mode 100644
index b6f43e85834c084..000000000000000
--- a/llvm/test/MC/X86/apx/user-msr-intel.s
+++ /dev/null
@@ -1,37 +0,0 @@
-# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-
-## urdmsr
-
-# CHECK: {evex} urdmsr r9, 123
-# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
- {evex} urdmsr r9, 123
-
-# CHECK: {evex} urdmsr r15, r9
-# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
- {evex} urdmsr r15, r9
-
-# CHECK: urdmsr r19, 123
-# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
- urdmsr r19, 123
-
-# CHECK: urdmsr r23, r19
-# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
- urdmsr r23, r19
-
-## uwrmsr
-
-# CHECK: {evex} uwrmsr 123, r9
-# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
- {evex} uwrmsr 123, r9
-
-# CHECK: {evex} uwrmsr r15, r9
-# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
- {evex} uwrmsr r15, r9
-
-# CHECK: uwrmsr 123, r19
-# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
- uwrmsr 123, r19
-
-# CHECK: uwrmsr r23, r19
-# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
- uwrmsr r23, r19
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 23886a3468243e5..9ee1472bdf5cc1b 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -214,8 +214,6 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
case IC_EVEX_OPSIZE_ADSIZE:
- case IC_EVEX_XS_ADSIZE:
- case IC_EVEX_XD_ADSIZE:
return false;
case IC_EVEX_K:
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
@@ -896,12 +894,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
for (unsigned index = 0; index < ATTR_max; ++index) {
o.indent(i * 2);
- if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
+ if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
o << "IC_EVEX_OPSIZE_ADSIZE";
- else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
- o << "IC_EVEX_XD_ADSIZE";
- else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
- o << "IC_EVEX_XS_ADSIZE";
else if (index & ATTR_EVEXNF) {
o << "IC_EVEX";
if (index & ATTR_REXW)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 18f961065c23320..fb430676c504b9f 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -188,7 +188,6 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
#define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
#define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
-#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -278,11 +277,14 @@ InstructionContext RecognizableInstr::insnContext() const {
}
// No L, no W
else if (OpPrefix == X86Local::PD) {
- insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
+ if (AdSize == X86Local::AdSize32)
+ insnContext = IC_EVEX_OPSIZE_ADSIZE;
+ else
+ insnContext = EVEX_KB(IC_EVEX_OPSIZE);
} else if (OpPrefix == X86Local::XD)
- insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
+ insnContext = EVEX_KB(IC_EVEX_XD);
else if (OpPrefix == X86Local::XS)
- insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
+ insnContext = EVEX_KB(IC_EVEX_XS);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB(IC_EVEX);
else {
>From 688a1e9ac1599da5d7d0f9cf0b7fc996e2c5582b Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 24 Jan 2024 18:42:21 -0800
Subject: [PATCH 12/13] restore changes
---
llvm/test/CodeGen/X86/usermsr-intrinsics.ll | 7 -------
1 file changed, 7 deletions(-)
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index 42fe8d4f3f7d841..b2a045a9349d1f7 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -1,13 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr | FileCheck %s --check-prefixes=X64
-; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr,+egpr | FileCheck %s --check-prefixes=EGPR
define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
; X64-LABEL: test_int_x86_urdmsr:
; X64: # %bb.0:
; X64-NEXT: urdmsr %rdi, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_urdmsr:
; EGPR: # %bb.0:
; EGPR-NEXT: urdmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
@@ -21,7 +19,6 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
; X64: # %bb.0:
; X64-NEXT: urdmsr $123, %rax # encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_urdmsr_const:
; EGPR: # %bb.0:
; EGPR-NEXT: urdmsr $123, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
@@ -37,7 +34,6 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: urdmsr %rax, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_urdmsr_const_i64:
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
@@ -55,7 +51,6 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_uwrmsr:
; EGPR: # %bb.0:
; EGPR-NEXT: uwrmsr %rsi, %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
@@ -69,7 +64,6 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rdi, $123 # encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_uwrmsr_const:
; EGPR: # %bb.0:
; EGPR-NEXT: uwrmsr %rdi, $123 # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
@@ -85,7 +79,6 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
-;
; EGPR-LABEL: test_int_x86_uwrmsr_const_i64:
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
>From 989c592a1bacdfbb67ff5007c18d06716ac2b569 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 24 Jan 2024 19:00:21 -0800
Subject: [PATCH 13/13] Fix error
---
.../Support/X86DisassemblerDecoderCommon.h | 2 +
.../X86/Disassembler/X86Disassembler.cpp | 3 ++
llvm/lib/Target/X86/X86InstrSystem.td | 41 ++++++++++++-------
llvm/test/CodeGen/X86/usermsr-intrinsics.ll | 7 ++++
.../test/MC/Disassembler/X86/apx/user-msr.txt | 38 +++++++++++++++++
llvm/test/MC/X86/apx/user-msr-att.s | 41 +++++++++++++++++++
llvm/test/MC/X86/apx/user-msr-intel.s | 37 +++++++++++++++++
llvm/utils/TableGen/X86DisassemblerTables.cpp | 8 +++-
llvm/utils/TableGen/X86RecognizableInstr.cpp | 10 ++---
9 files changed, 166 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/user-msr.txt
create mode 100644 llvm/test/MC/X86/apx/user-msr-att.s
create mode 100644 llvm/test/MC/X86/apx/user-msr-intel.s
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
index 3aceb247a26c21e..0dc974ea9efd8d1 100644
--- a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
+++ b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -140,7 +140,9 @@ enum attributeBits {
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
+ ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
+ ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index ce7f707066bb07e..5f8526136106645 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -941,6 +941,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
case VEX_LOB_MAP6:
insn->opcodeType = MAP6;
return consume(insn, insn->opcode);
+ case VEX_LOB_MAP7:
+ insn->opcodeType = MAP7;
+ return consume(insn, insn->opcode);
}
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 74b478212f17487..a7899a2492b8823 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -436,21 +436,34 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
}
-let Predicates = [HasUSERMSR], mayLoad = 1 in {
- def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
- "urdmsr\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
- def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
- "urdmsr\t{$imm, $dst|$dst, $imm}",
- [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
+multiclass Urdwrmsr<Map rrmap, string suffix> {
+ let mayLoad = 1 in {
+ let OpMap = rrmap in
+ def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+ "urdmsr\t{$src, $dst|$dst, $src}",
+ [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
+ def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
+ "urdmsr\t{$imm, $dst|$dst, $imm}",
+ [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
+ T_MAP7, VEX, XD, NoCD8;
}
-let Predicates = [HasUSERMSR], mayStore = 1 in {
- def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
- "uwrmsr\t{$src2, $src1|$src1, $src2}",
- [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
- def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
- "uwrmsr\t{$src, $imm|$imm, $src}",
- [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
+ let mayStore = 1 in {
+ let OpMap = rrmap in
+ def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+ "uwrmsr\t{$src2, $src1|$src1, $src2}",
+ [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
+ def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
+ "uwrmsr\t{$src, $imm|$imm, $src}",
+ [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
+ T_MAP7, VEX, XS, NoCD8;
+ }
+}
+
+let Predicates = [HasUSERMSR, NoEGPR] in
+ defm "" : Urdwrmsr<T8, "">;
+
+let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
+ defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index b2a045a9349d1f7..42fe8d4f3f7d841 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -1,11 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr,+egpr | FileCheck %s --check-prefixes=EGPR
define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
; X64-LABEL: test_int_x86_urdmsr:
; X64: # %bb.0:
; X64-NEXT: urdmsr %rdi, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_urdmsr:
; EGPR: # %bb.0:
; EGPR-NEXT: urdmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
@@ -19,6 +21,7 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
; X64: # %bb.0:
; X64-NEXT: urdmsr $123, %rax # encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_urdmsr_const:
; EGPR: # %bb.0:
; EGPR-NEXT: urdmsr $123, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
@@ -34,6 +37,7 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: urdmsr %rax, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_urdmsr_const_i64:
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
@@ -51,6 +55,7 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_uwrmsr:
; EGPR: # %bb.0:
; EGPR-NEXT: uwrmsr %rsi, %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
@@ -64,6 +69,7 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT: uwrmsr %rdi, $123 # encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_uwrmsr_const:
; EGPR: # %bb.0:
; EGPR-NEXT: uwrmsr %rdi, $123 # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
@@ -79,6 +85,7 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; X64-NEXT: # imm = 0x1FFFFFFFF
; X64-NEXT: uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; X64-NEXT: retq # encoding: [0xc3]
+;
; EGPR-LABEL: test_int_x86_uwrmsr_const_i64:
; EGPR: # %bb.0:
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/X86/apx/user-msr.txt b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
new file mode 100644
index 000000000000000..60cdab132485c61
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/user-msr.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+## urdmsr
+
+# ATT: urdmsr $123, %r9
+# INTEL: urdmsr r9, 123
+0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r9, %r15
+# INTEL: urdmsr r15, r9
+0x62,0x54,0x7f,0x08,0xf8,0xf9
+
+# ATT: urdmsr $123, %r19
+# INTEL: urdmsr r19, 123
+0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: urdmsr %r19, %r23
+# INTEL: urdmsr r23, r19
+0x62,0xec,0x7f,0x08,0xf8,0xfb
+
+## uwrmsr
+
+# ATT: uwrmsr %r9, $123
+# INTEL: uwrmsr 123, r9
+0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r9, %r15
+# INTEL: uwrmsr r15, r9
+0x62,0x54,0x7e,0x08,0xf8,0xf9
+
+# ATT: uwrmsr %r19, $123
+# INTEL: uwrmsr 123, r19
+0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
+
+# ATT: uwrmsr %r19, %r23
+# INTEL: uwrmsr r23, r19
+0x62,0xec,0x7e,0x08,0xf8,0xfb
diff --git a/llvm/test/MC/X86/apx/user-msr-att.s b/llvm/test/MC/X86/apx/user-msr-att.s
new file mode 100644
index 000000000000000..59df5895d53ec1d
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-att.s
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-8: error:
+# ERROR-NOT: error:
+
+## urdmsr
+
+# CHECK: {evex} urdmsr $123, %r9
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr $123, %r9
+
+# CHECK: {evex} urdmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr %r9, %r15
+
+# CHECK: urdmsr $123, %r19
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr $123, %r19
+
+# CHECK: urdmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr %r19, %r23
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr %r9, $123
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr %r9, $123
+
+# CHECK: {evex} uwrmsr %r9, %r15
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr %r9, %r15
+
+# CHECK: uwrmsr %r19, $123
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr %r19, $123
+
+# CHECK: uwrmsr %r19, %r23
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr %r19, %r23
diff --git a/llvm/test/MC/X86/apx/user-msr-intel.s b/llvm/test/MC/X86/apx/user-msr-intel.s
new file mode 100644
index 000000000000000..b6f43e85834c084
--- /dev/null
+++ b/llvm/test/MC/X86/apx/user-msr-intel.s
@@ -0,0 +1,37 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+## urdmsr
+
+# CHECK: {evex} urdmsr r9, 123
+# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} urdmsr r9, 123
+
+# CHECK: {evex} urdmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
+ {evex} urdmsr r15, r9
+
+# CHECK: urdmsr r19, 123
+# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ urdmsr r19, 123
+
+# CHECK: urdmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
+ urdmsr r23, r19
+
+## uwrmsr
+
+# CHECK: {evex} uwrmsr 123, r9
+# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
+ {evex} uwrmsr 123, r9
+
+# CHECK: {evex} uwrmsr r15, r9
+# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
+ {evex} uwrmsr r15, r9
+
+# CHECK: uwrmsr 123, r19
+# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
+ uwrmsr 123, r19
+
+# CHECK: uwrmsr r23, r19
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
+ uwrmsr r23, r19
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 9ee1472bdf5cc1b..23886a3468243e5 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -214,6 +214,8 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
case IC_EVEX_OPSIZE_ADSIZE:
+ case IC_EVEX_XS_ADSIZE:
+ case IC_EVEX_XD_ADSIZE:
return false;
case IC_EVEX_K:
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
@@ -894,8 +896,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
for (unsigned index = 0; index < ATTR_max; ++index) {
o.indent(i * 2);
- if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+ if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
o << "IC_EVEX_OPSIZE_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
+ o << "IC_EVEX_XD_ADSIZE";
+ else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
+ o << "IC_EVEX_XS_ADSIZE";
else if (index & ATTR_EVEXNF) {
o << "IC_EVEX";
if (index & ATTR_REXW)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index fb430676c504b9f..18f961065c23320 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -188,6 +188,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
#define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
#define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
+#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
InstructionContext RecognizableInstr::insnContext() const {
InstructionContext insnContext;
@@ -277,14 +278,11 @@ InstructionContext RecognizableInstr::insnContext() const {
}
// No L, no W
else if (OpPrefix == X86Local::PD) {
- if (AdSize == X86Local::AdSize32)
- insnContext = IC_EVEX_OPSIZE_ADSIZE;
- else
- insnContext = EVEX_KB(IC_EVEX_OPSIZE);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
} else if (OpPrefix == X86Local::XD)
- insnContext = EVEX_KB(IC_EVEX_XD);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
else if (OpPrefix == X86Local::XS)
- insnContext = EVEX_KB(IC_EVEX_XS);
+ insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
else if (OpPrefix == X86Local::PS)
insnContext = EVEX_KB(IC_EVEX);
else {
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