[flang-commits] [clang-tools-extra] [flang] [clang] [compiler-rt] [llvm] [RISCV][MC] Add experimental support of Zaamo and Zalrsc (PR #78970)
Wang Pengcheng via flang-commits
flang-commits at lists.llvm.org
Wed Jan 24 19:59:46 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/78970
>From 8cc71cb7ddb2e6691d31138ae2ef683a0690e171 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Mon, 22 Jan 2024 21:11:42 +0800
Subject: [PATCH 1/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Created using spr 1.3.4
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
.../test/Preprocessor/riscv-target-features.c | 18 ++
llvm/docs/RISCVUsage.rst | 2 +
llvm/lib/Support/RISCVISAInfo.cpp | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++-
llvm/test/CodeGen/RISCV/attributes.ll | 8 +
llvm/test/MC/RISCV/rv32i-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zaamo-invalid.s | 11 ++
llvm/test/MC/RISCV/rv32zaamo-valid.s | 122 ++++++++++++++
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 7 +
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 36 ++++
llvm/test/MC/RISCV/rv64zaamo-invalid.s | 11 ++
llvm/test/MC/RISCV/rv64zaamo-valid.s | 157 ++++++++++++++++++
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 7 +
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 42 +++++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 2 +
16 files changed, 452 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/RISCV/rv32zaamo-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zaamo-valid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zaamo-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zaamo-valid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-valid.s
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index c71b2e9eeb6c17..9af9bdd1d74e9d 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -175,7 +175,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__riscv_muldiv");
}
- if (ISAInfo->hasExtension("a")) {
+ if (ISAInfo->hasExtension("a") || ISAInfo->hasExtension("zaamo")) {
Builder.defineMacro("__riscv_atomic");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 5fde5ccdbeacfb..38473d07004a57 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -141,7 +141,9 @@
// Experimental extensions
+// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
+// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
@@ -1307,6 +1309,14 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}}
// Experimental extensions
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zaamo0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zaamo0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
+// CHECK-ZAAMO-EXT: __riscv_atomic 1
+// CHECK-ZAAMO-EXT: __riscv_zaamo 1000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zacas1p0 -x c -E -dM %s \
@@ -1316,6 +1326,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zalrsc0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
+// RUN: %clang --target=riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zalrsc0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 1000{{$}}
+
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 6fdc945ad27078..005e9f1d732444 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -100,6 +100,8 @@ on support follow.
``V`` Supported
``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Zaamo`` Supported
+ ``Zalrsc`` Supported
``Zawrs`` Assembly Support
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 3c02492e99f1db..a5f00d14c94aa0 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -191,7 +191,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
+ {"zaamo", {0, 1}},
{"zacas", {1, 0}},
+ {"zalrsc", {0, 1}},
{"zcmop", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index cbb096ba20ae67..7c3a7a1937e2b2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -168,6 +168,18 @@ def FeatureStdExtZa64rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs", "true",
def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs", "true",
"'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+def FeatureStdExtZaamo
+ : SubtargetFeature<"experimental-zaamo", "HasStdExtZaamo", "true",
+ "'Zaamo' (Atomic Memory Operations)">;
+def HasStdExtZaamo : Predicate<"Subtarget->hasStdExtZaamo()">,
+ AssemblerPredicate<(all_of FeatureStdExtZaamo),
+ "'Zaamo' (Atomic Memory Operations)">;
+def HasStdExtAOrZaamo
+ : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
+ AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
+ "'A' (Atomic Instructions) or "
+ "'Zaamo' (Atomic Memory Operations)">;
+
def FeatureStdExtZacas
: SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
@@ -176,6 +188,18 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
+def FeatureStdExtZalrsc
+ : SubtargetFeature<"experimental-zalrsc", "HasStdExtZalrsc", "true",
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+def HasStdExtZalrsc : Predicate<"Subtarget->hasStdExtZalrsc()">,
+ AssemblerPredicate<(all_of FeatureStdExtZalrsc),
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+def HasStdExtAOrZalrsc
+ : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
+ AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
+ "'A' (Atomic Instructions) or "
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
@@ -1105,7 +1129,7 @@ def FeatureForcedAtomics : SubtargetFeature<
"forced-atomics", "HasForcedAtomics", "true",
"Assume that lock-free native-width atomics are available">;
def HasAtomicLdSt
- : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
+ : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b90bef7525379d..e5be0267d134ea 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -93,7 +93,9 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
@@ -195,7 +197,9 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV64ZAAMO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
; CHECK: .attribute 4, 16
@@ -292,7 +296,9 @@
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
+; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p1"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
+; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p1"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
@@ -393,7 +399,9 @@
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
+; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p1"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
+; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p1"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index c5e0657b838094..25a419cbefd4d0 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -170,7 +170,7 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Instruction not in the base ISA
div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}}
-amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions){{$}}
+amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations){{$}}
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}}
diff --git a/llvm/test/MC/RISCV/rv32zaamo-invalid.s b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
new file mode 100644
index 00000000000000..f5974828d90c4a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
+amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
+amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# Only .aq, .rl, and .aqrl suffixes are valid
+amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
diff --git a/llvm/test/MC/RISCV/rv32zaamo-valid.s b/llvm/test/MC/RISCV/rv32zaamo-valid.s
new file mode 100644
index 00000000000000..18b31cd0083363
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zaamo-valid.s
@@ -0,0 +1,122 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zaamo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zaamo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zaamo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zaamo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zaamo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zaamo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
+amoswap.w a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00]
+amoadd.w a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20]
+amoxor.w a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60]
+amoand.w a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40]
+amoor.w a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81]
+amomin.w a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1]
+amomax.w s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1]
+amominu.w s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1]
+amomaxu.w s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.aq a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c]
+amoswap.w.aq a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.aq a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04]
+amoadd.w.aq a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.aq a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24]
+amoxor.w.aq a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.aq a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64]
+amoand.w.aq a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44]
+amoor.w.aq a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.aq a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85]
+amomin.w.aq a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.aq s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5]
+amomax.w.aq s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.aq s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5]
+amominu.w.aq s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.aq s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5]
+amomaxu.w.aq s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.rl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a]
+amoswap.w.rl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.rl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02]
+amoadd.w.rl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.rl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22]
+amoxor.w.rl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.rl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62]
+amoand.w.rl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.rl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42]
+amoor.w.rl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.rl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83]
+amomin.w.rl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.rl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3]
+amomax.w.rl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.rl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3]
+amominu.w.rl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.rl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3]
+amomaxu.w.rl s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.aqrl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e]
+amoswap.w.aqrl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.aqrl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06]
+amoadd.w.aqrl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.aqrl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26]
+amoxor.w.aqrl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.aqrl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66]
+amoand.w.aqrl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.aqrl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46]
+amoor.w.aqrl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.aqrl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87]
+amomin.w.aqrl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.aqrl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7]
+amomax.w.aqrl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.aqrl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7]
+amominu.w.aqrl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7]
+amomaxu.w.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-invalid.s b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
new file mode 100644
index 00000000000000..01e5a19a335aff
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalrsc < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-valid.s b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
new file mode 100644
index 00000000000000..08c84f88979290
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalrsc -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalrsc -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalrsc < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zalrsc -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalrsc < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zalrsc -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
+lr.w t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
+lr.w.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
+lr.w.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
+lr.w.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
+sc.w t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
+sc.w.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
+sc.w.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
+sc.w.aqrl t3, t2, (t1)
diff --git a/llvm/test/MC/RISCV/rv64zaamo-invalid.s b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
new file mode 100644
index 00000000000000..d196de83034261
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zaamo < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
+amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
+amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# Only .aq, .rl, and .aqrl suffixes are valid
+amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
diff --git a/llvm/test/MC/RISCV/rv64zaamo-valid.s b/llvm/test/MC/RISCV/rv64zaamo-valid.s
new file mode 100644
index 00000000000000..01bb8f56c120af
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zaamo-valid.s
@@ -0,0 +1,157 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zaamo -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zaamo < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zaamo -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d s5, s4, (s3)
+
+
+# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.aq a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.aq a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.aq a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.aq a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.aq a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.aq a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.aq s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.aq s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.aq s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.rl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.rl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.rl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.rl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.rl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.rl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.rl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.rl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.rl s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.aqrl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.aqrl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.aqrl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.aqrl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.aqrl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.aqrl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.aqrl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.aqrl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-invalid.s b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
new file mode 100644
index 00000000000000..5a756847ac9636
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalrsc < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-valid.s b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
new file mode 100644
index 00000000000000..2c338afcdb5d68
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalrsc -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalrsc < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zalrsc -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalrsc < %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aqrl t3, t2, (t1)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 9b7112fa2bfeb5..c1578c19a4976c 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -795,7 +795,9 @@ Experimental extensions
zicfiss 0.4
zicond 1.0
zimop 0.1
+ zaamo 0.1
zacas 1.0
+ zalrsc 0.1
zfbfmin 1.0
zcmop 0.2
ztso 0.1
>From 457472bcaa74d76ee44ece2b8ae6a0a2268d1263 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Mon, 22 Jan 2024 21:23:57 +0800
Subject: [PATCH 2/7] disable clang-format
Created using spr 1.3.4
---
llvm/lib/Support/RISCVISAInfo.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index a5f00d14c94aa0..715c29a9e15afe 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -190,6 +190,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
};
// NOTE: This table should be sorted alphabetically by extension name.
+// clang-format off
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zaamo", {0, 1}},
{"zacas", {1, 0}},
@@ -211,6 +212,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zvfbfmin", {1, 0}},
{"zvfbfwma", {1, 0}},
};
+// clang-format on
static void verifyTables() {
#ifndef NDEBUG
>From 39c659abfd268e4d744755fb07600356a7966f00 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 23 Jan 2024 15:47:04 +0800
Subject: [PATCH 3/7] Address comments
Created using spr 1.3.4
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
clang/test/Preprocessor/riscv-target-features.c | 1 -
llvm/docs/RISCVUsage.rst | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +-
4 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 9af9bdd1d74e9d..c71b2e9eeb6c17 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -175,7 +175,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__riscv_muldiv");
}
- if (ISAInfo->hasExtension("a") || ISAInfo->hasExtension("zaamo")) {
+ if (ISAInfo->hasExtension("a")) {
Builder.defineMacro("__riscv_atomic");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 38473d07004a57..8283c31c0abfa4 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1315,7 +1315,6 @@
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zaamo0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_atomic 1
// CHECK-ZAAMO-EXT: __riscv_zaamo 1000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 005e9f1d732444..bb4caebeea529d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -100,8 +100,8 @@ on support follow.
``V`` Supported
``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
- ``Zaamo`` Supported
- ``Zalrsc`` Supported
+ ``Zaamo`` Assembly Support
+ ``Zalrsc`` Assembly Support
``Zawrs`` Assembly Support
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 7c3a7a1937e2b2..8ca7cdc2a54ad9 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1129,7 +1129,7 @@ def FeatureForcedAtomics : SubtargetFeature<
"forced-atomics", "HasForcedAtomics", "true",
"Assume that lock-free native-width atomics are available">;
def HasAtomicLdSt
- : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">;
+ : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
>From 8402c2789649a8875bb5b101bb7f38440a7fbec8 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 23 Jan 2024 16:33:30 +0800
Subject: [PATCH 4/7] Update Predicates
Created using spr 1.3.4
---
clang/test/Preprocessor/riscv-target-features.c | 4 ++--
llvm/docs/RISCVUsage.rst | 5 +++--
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 14 ++++++++++----
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++----
llvm/unittests/Support/RISCVISAInfoTest.cpp | 4 ++--
6 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 8283c31c0abfa4..da83e344315187 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1315,7 +1315,7 @@
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zaamo0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 1000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zacas1p0 -x c -E -dM %s \
@@ -1331,7 +1331,7 @@
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zalrsc0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 1000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index bb4caebeea529d..3d2ba3334e9e08 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -100,8 +100,6 @@ on support follow.
``V`` Supported
``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Za64rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
- ``Zaamo`` Assembly Support
- ``Zalrsc`` Assembly Support
``Zawrs`` Assembly Support
``Zba`` Supported
``Zbb`` Supported
@@ -248,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zcmop``
LLVM implements the `v0.2 proposed specification <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>`__.
+``experimental-zaamo``, ``experimental-zalrsc``
+ LLVM implements the `v0.2 proposed specification <https://github.com/riscv/riscv-zaamo-zalrsc/releases/tag/v0.2>`__.
+
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Vendor Extensions
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 715c29a9e15afe..32b4ff5de86f1e 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -192,9 +192,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
// NOTE: This table should be sorted alphabetically by extension name.
// clang-format off
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
- {"zaamo", {0, 1}},
+ {"zaamo", {0, 2}},
{"zacas", {1, 0}},
- {"zalrsc", {0, 1}},
+ {"zalrsc", {0, 2}},
{"zcmop", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 44552c00c62e55..36842ceb49bfb8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -47,10 +47,13 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtA], IsSignExtendingOpW = 1 in {
+let Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1 in {
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
+} // Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1
+
+let Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1 in {
defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
@@ -69,12 +72,15 @@ defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
-} // Predicates = [HasStdExtA]
+} // Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1
-let Predicates = [HasStdExtA, IsRV64] in {
+let Predicates = [HasStdExtAOrZalrsc, IsRV64] in {
defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">,
Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
+} // Predicates = [HasStdExtAOrZalrsc, IsRV64]
+
+let Predicates = [HasStdExtAOrZaamo, IsRV64] in {
defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
@@ -93,7 +99,7 @@ defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
-} // Predicates = [HasStdExtA, IsRV64]
+} // Predicates = [HasStdExtAOrZaamo, IsRV64]
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index e5be0267d134ea..ed1ab5a74f5c4f 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -296,9 +296,9 @@
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p1"
+; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p2"
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
-; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p1"
+; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
@@ -399,9 +399,9 @@
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
-; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p1"
+; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p2"
; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
-; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p1"
+; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p2"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
define i32 @addi(i32 %a) {
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index c1578c19a4976c..a595526dd24a9a 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -795,9 +795,9 @@ Experimental extensions
zicfiss 0.4
zicond 1.0
zimop 0.1
- zaamo 0.1
+ zaamo 0.2
zacas 1.0
- zalrsc 0.1
+ zalrsc 0.2
zfbfmin 1.0
zcmop 0.2
ztso 0.1
>From 97dd221b6af83d37a4abb1be4f11e7eeec62e363 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 23 Jan 2024 16:59:41 +0800
Subject: [PATCH 5/7] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20ch?=
=?UTF-8?q?anges=20introduced=20through=20rebase?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
[skip ci]
---
.../{rv32a-invalid.s => rv32zaamo-invalid.s} | 7 ----
.../{rv32a-valid.s => rv32zaamo-valid.s} | 26 ------------
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 7 ++++
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 36 ++++++++++++++++
.../{rv64a-invalid.s => rv64zaamo-invalid.s} | 4 --
.../{rv64a-valid.s => rv64zaamo-valid.s} | 34 ---------------
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 7 ++++
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 42 +++++++++++++++++++
8 files changed, 92 insertions(+), 71 deletions(-)
rename llvm/test/MC/RISCV/{rv32a-invalid.s => rv32zaamo-invalid.s} (71%)
rename llvm/test/MC/RISCV/{rv32a-valid.s => rv32zaamo-valid.s} (85%)
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-valid.s
rename llvm/test/MC/RISCV/{rv64a-invalid.s => rv64zaamo-invalid.s} (78%)
rename llvm/test/MC/RISCV/{rv64a-valid.s => rv64zaamo-valid.s} (83%)
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-valid.s
diff --git a/llvm/test/MC/RISCV/rv32a-invalid.s b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
similarity index 71%
rename from llvm/test/MC/RISCV/rv32a-invalid.s
rename to llvm/test/MC/RISCV/rv32zaamo-invalid.s
index 34d51fc30ca210..f6183fbc8a1f13 100644
--- a/llvm/test/MC/RISCV/rv32a-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
@@ -4,15 +4,8 @@
amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
-
-# Note: errors for use of RV64A instructions for RV32 are checked in
-# rv64a-valid.s
diff --git a/llvm/test/MC/RISCV/rv32a-valid.s b/llvm/test/MC/RISCV/rv32zaamo-valid.s
similarity index 85%
rename from llvm/test/MC/RISCV/rv32a-valid.s
rename to llvm/test/MC/RISCV/rv32zaamo-valid.s
index 1f66680c27114f..ea1ae79558443e 100644
--- a/llvm/test/MC/RISCV/rv32a-valid.s
+++ b/llvm/test/MC/RISCV/rv32zaamo-valid.s
@@ -9,32 +9,6 @@
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
-lr.w t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
-lr.w.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
-lr.w.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
-lr.w.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
-sc.w t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
-sc.w.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
-sc.w.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
-sc.w.aqrl t3, t2, (t1)
-
# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
amoswap.w a4, ra, (s0)
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-invalid.s b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
new file mode 100644
index 00000000000000..61cfc614b7c420
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-valid.s b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
new file mode 100644
index 00000000000000..0d4881a4b45a7b
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
+lr.w t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
+lr.w.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
+lr.w.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
+lr.w.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
+sc.w t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
+sc.w.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
+sc.w.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
+sc.w.aqrl t3, t2, (t1)
diff --git a/llvm/test/MC/RISCV/rv64a-invalid.s b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
similarity index 78%
rename from llvm/test/MC/RISCV/rv64a-invalid.s
rename to llvm/test/MC/RISCV/rv64zaamo-invalid.s
index 2816f434e47066..70a4e557755baa 100644
--- a/llvm/test/MC/RISCV/rv64a-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
@@ -4,12 +4,8 @@
amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
# Only .aq, .rl, and .aqrl suffixes are valid
amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64a-valid.s b/llvm/test/MC/RISCV/rv64zaamo-valid.s
similarity index 83%
rename from llvm/test/MC/RISCV/rv64a-valid.s
rename to llvm/test/MC/RISCV/rv64zaamo-valid.s
index 3276b397f7194c..73cdc55584341c 100644
--- a/llvm/test/MC/RISCV/rv64a-valid.s
+++ b/llvm/test/MC/RISCV/rv64zaamo-valid.s
@@ -7,40 +7,6 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
-# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aqrl t3, t2, (t1)
-
# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-invalid.s b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
new file mode 100644
index 00000000000000..0be009725ed82a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-valid.s b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
new file mode 100644
index 00000000000000..d4c87523b71c1e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aqrl t3, t2, (t1)
>From 503c829eb9acaf4352df3ace0e0d938e820d86d0 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 25 Jan 2024 11:57:50 +0800
Subject: [PATCH 6/7] Add an error test for lr/sc
Created using spr 1.3.4
---
llvm/test/MC/RISCV/rv32i-invalid.s | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index 25a419cbefd4d0..1910a5946fba18 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -171,6 +171,7 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Instruction not in the base ISA
div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}}
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations){{$}}
+lr.d t0, (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zalrsc' (Load-Reserved/Store-Conditional){{$}}
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}}
>From 842c43b7de3c03db17302d3ad9fc0ba0fdc94c2a Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 25 Jan 2024 11:59:33 +0800
Subject: [PATCH 7/7] Use .w since it is a rv32 test
Created using spr 1.3.4
---
llvm/test/MC/RISCV/rv32i-invalid.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s
index 1910a5946fba18..80a59df94e36a3 100644
--- a/llvm/test/MC/RISCV/rv32i-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-invalid.s
@@ -171,7 +171,7 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Instruction not in the base ISA
div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}}
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations){{$}}
-lr.d t0, (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zalrsc' (Load-Reserved/Store-Conditional){{$}}
+lr.w t0, (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zalrsc' (Load-Reserved/Store-Conditional){{$}}
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}}
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