[flang-commits] [flang] a4e67de - [flang] update ppc-vec-store-elem-order.f90 after #74709 (NFC) (#75064)

[via flang-commits]

Author: kkwli
Date: 2023-12-11T12:32:13-05:00
New Revision: a4e67de96f0a9833756b6c79fff3cd6ee459fee0

URL: https://github.com/llvm/llvm-project/commit/a4e67de96f0a9833756b6c79fff3cd6ee459fee0
DIFF: https://github.com/llvm/llvm-project/commit/a4e67de96f0a9833756b6c79fff3cd6ee459fee0.diff

LOG: [flang] update ppc-vec-store-elem-order.f90 after #74709 (NFC) (#75064)

Added: 
    

Modified: 
    flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90

Removed: 
    


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diff  --git a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
index 494ed21f4fe928..caf6d5463a8336 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
@@ -67,10 +67,10 @@ subroutine vec_xstd2_test(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
@@ -93,10 +93,10 @@ subroutine vec_xstw4_test(arg1, arg2, arg3, i)
 
 ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
-! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
-! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
-! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
-! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
+! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
+! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
+! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
+! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2