[cfe-dev] IEEE MICRO Special Issue on Compiling for Accelerators

Chris Lattner via cfe-dev cfe-dev at lists.llvm.org
Mon Jun 21 12:24:20 PDT 2021


Hi Guido,

Our policy for the LLVM/Clang mailing lists is that they need to be specifically on topic for LLVM.  Please do not send generic compiler-related conference CFP’s here.  Thank you!

-Chris

> On Jun 21, 2021, at 12:06 PM, Guido Araujo via cfe-dev <cfe-dev at lists.llvm.org> wrote:
> 
> Call for Papers:  IEEE MICRO Special Issue on Compiling for Accelerators <https://www.computer.org/digital-library/magazines/mi/call-for-papers-special-issue-on-compiling-for-accelerators>
>  
> Submission Deadline: December 15, 2021
>  
> Scope and Topics
>  
> Hardware accelerators are rapidly becoming a central architectural feature to improve computation power performance. CPU ISA extensions, custom-designed engines, and FPGA-based systems have been proposed as acceleration architectures to improve program execution in scientific, machine-learning, database, and other application domains. Although much effort has been devoted to the design of accelerators, there is still a large gap of knowledge on how to make effective use of and compile for such architectures. This special issue of IEEE Micro will explore academic and industrial research on topics that relate to compiling for accelerators.
>  
> Topics of interest include, but are not limited to:
>  
> ●      Compiling for CPU ISA extensions
> ●      Code generation for neural processing units
> ●      Compiling for neural network training
> ●      Programming linear algebra engines
> ●      Code generation and programming for database accelerators
> ●      Processor-accelerator interface design and programmability
> ●      Compiling for energy efficiency
> ●      Pattern matching and code replacement for acceleration instructions
> ●      High-level synthesis design of custom engines
> ●      DSL and parallel programming models for accelerators
> ●      Compiler intermediate representation (IR) and optimization techniques for accelerators
> ●      Programming FPGAs for custom computing engines
> ●      Tools and libraries to support code generation for accelerators
>  
> Important Dates
>  
> ●      Submission Deadline: December 15, 2021
> ●      Initial notifications: March 15, 2022
> ●      Revised papers due: April 8, 2022
> ●      Final notifications: May 13, 2022
> ●      Final versions due: May 31, 2022
> ●      Publication: July/August 2022
>  
> Submission Guidelines
>  
> Please see the Author Information page <https://www.computer.org/csdl/magazine/mi/write-for-us/14289?title=Author%20Information&periodical=IEEE%20Micro> and the Magazine Peer Review page  <https://www.computer.org/publications/author-resources/peer-review/magazines>for more information. Please submit electronically through ScholarOne Manuscripts <https://mc.manuscriptcentral.com/cs-ieee>, selecting this special-issue option. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication.
>  
> Questions?
>  
> Contact guest editors Guido Araujo and Lucas Wanner at micro4-22 at computer.org <mailto:micro4-22 at computer.org>, or the editor-in-chief Lizy John at ljohn at ece.utexas.edu <mailto:ljohn at ece.utexas.edu>.
> Please direct ScholarOne-related questions to the IEEE Micro magazine assistant at micro-ma at computer.org <mailto:micro-ma at computer.org>.
>  
> ==========================================================
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