[cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon

[JF Bastien via cfe-dev]

These? https://docs.microsoft.com/en-us/cpp/intrinsics/arm-intrinsics?view=vs-2017#IsoVolatileLoadStore <https://docs.microsoft.com/en-us/cpp/intrinsics/arm-intrinsics?view=vs-2017#IsoVolatileLoadStore>

__int16 __iso_volatile_load16(const volatile __int16 * Location)
__int32 __iso_volatile_load32(const volatile __int32 * Location)
__int64 __iso_volatile_load64(const volatile __int64 * Location)
__int8 __iso_volatile_load8(const volatile __int8 * Location)

void __iso_volatile_store16(volatile __int16 * Location, __int16 Value)
void __iso_volatile_store32(volatile __int32 * Location, __int32 Value)
void __iso_volatile_store64(volatile __int64 * Location, __int64 Value)
void __iso_volatile_store8(volatile __int8 * Location, __int8 Value)

Seems fine, given how MSVC’s volatiles on x86 were traditionally seq_cst when they could. I think the above match the LLVM IR semantics precisely.

I think you should add type-generic versions as well. Then you’ve got a nice builtin for volatile_load<T> / volatile_store<T> <http://wg21.link/P1382>, and who doesn’t love C++ library features that require compiler support? Right Billy? 😁



> On Mar 19, 2019, at 1:32 PM, Billy O'Neal (VC LIBS) via cfe-dev <cfe-dev at lists.llvm.org> wrote:
> 
> I think Clang has those already implemented for ARM (since our <atomic> compiles there) but we are looking to use them instead of cmpxchg8b to implement load of atomic<8 bytes> on x86 soon.
> 
> Billy3
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