[cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?

[Ulrich Weigand via cfe-dev]

Oh, and other thing:   Are you planning to attend the upcoming LLVM
developer's meeting in Bristol?  I thought it might be good idea to get all
parties interested in this feature together in person, if we're at the same
meeting anyway.  So I was thinking of submitting a proposal for a BoF
session on this topic ...


Mit freundlichen Gruessen / Best Regards

Ulrich Weigand

--
  Dr. Ulrich Weigand | Phone: +49-7031/16-3727
  STSM, GNU/Linux compilers and toolchain
  IBM Deutschland Research & Development GmbH
  Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
  Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht
Stuttgart, HRB 243294



From:	"Kaylor, Andrew" <andrew.kaylor at intel.com>
To:	Ulrich Weigand <Ulrich.Weigand at de.ibm.com>,
            "kpn at neutralgood.org" <kpn at neutralgood.org>
Cc:	Hal Finkel <hfinkel at anl.gov>, Richard Smith
            <richard at metafoo.co.uk>, "bob.huemmer at sas.com"
            <bob.huemmer at sas.com>, "bumblebritches57 at gmail.com"
            <bumblebritches57 at gmail.com>, "cfe-dev at lists.llvm.org"
            <cfe-dev at lists.llvm.org>, llvm-dev <llvm-dev at lists.llvm.org>
Date:	09.01.2018 19:55
Subject:	RE: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?



I think we’re going to need to create a new mechanism to communicate strict
FP modes to the backend. I think we need to avoid doing anything that will
require re-inventing or duplicating all of the pattern matching that goes
on in instruction selection (which is the reason we’re currently dropping
that information). I’m out of my depth on this transition, but I think
maybe we could handle it with some kind of attribute on the MBB.

In C/C++, at least, it’s my understanding that the pragmas always apply at
the scope-level (as opposed to having the possibility of being
instruction-specific), and we’ve previously agreed that our implementation
will really need to apply the rules across entire functions in the sense
that if any part of a function uses the constrained intrinsics all FP
operations in the function will need to use them (though different metadata
arguments may be used in different scopes). So I think that opens our
options a bit.

Regarding constant folding, I think you are correct that it isn’t happening
anywhere in the backends at the moment. There is some constant folding done
during instruction selection, but the existing mechanism prevents that. My
concern is that given LLVM’s development model, if there is nothing in
place to prevent constant folding and no consensus that it shouldn’t be
allowed then we should probably believe that someone will eventually do it.

-Andy

From: Ulrich Weigand [mailto:Ulrich.Weigand at de.ibm.com]
Sent: Tuesday, January 09, 2018 9:59 AM
To: Kaylor, Andrew <andrew.kaylor at intel.com>; kpn at neutralgood.org
Cc: Hal Finkel <hfinkel at anl.gov>; Richard Smith <richard at metafoo.co.uk>;
bob.huemmer at sas.com; bumblebritches57 at gmail.com; wei.ding2 at amd.com;
cfe-dev at lists.llvm.org; llvm-dev <llvm-dev at lists.llvm.org>
Subject: Re: [cfe-dev] Why is #pragma STDC FENV_ACCESS not supported?



Andrew Kaylor wrote:

>In general, the current "strict FP" handling stops at instruction
>selection. At the MachineIR level we don't currently have a mechanism
>to prevent inappropriate optimizations based on floating point
>constraints, or indeed to convey such constraints to the backend.
>Implicit register use modeling may provide some restriction on some
>architectures, but this is definitely lacking for X86 targets. On the
>other hand, I'm not aware of any specific current problems, so in many
>cases we may "get lucky" and have the correct thing happen by chance.
>Obviously that's not a viable long term solution. I have a rough plan
>for adding improved register modeling to the X86 backend, which should
>take care of instruction scheduling issues, but we'd still need a
>mechanism to prevent constant folding optimizations and such.

Given that Kevin intends to target SystemZ, I'll be happy to work on the
SystemZ back-end support for this feature. I agree that we should be using
implicit control register dependencies, which will at least prevent moving
floating-point operations across instructions that e.g. change rounding
modes. However, the main property we need to model is that floating-point
operations may *trap*. I guess this can be done using UnmodeledSideEffects,
but I'm not quite clear on how to make this dependent on whether or not a
"strict" operation is requested (without duplicating all the instruction
patterns ...).

Once we do use something like UnmodeledSideEffects, I think MachineIR
passes should handle everything correctly; in the end, the requirements are
not really different from those of other trapping instructions. B.t.w. I
don't think anybody does constant folding on floating-point constants at
the MachineIR level anyway ... have you seen this anywhere?


Mit freundlichen Gruessen / Best Regards

Ulrich Weigand

--
Dr. Ulrich Weigand | Phone: +49-7031/16-3727
STSM, GNU/Linux compilers and toolchain
IBM Deutschland Research & Development GmbH
Vorsitzende des Aufsichtsrats: Martina Koederitz | Geschäftsführung: Dirk
Wittkopp
Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart,
HRB 243294





-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/cfe-dev/attachments/20180209/a5046b72/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: graycol.gif
Type: image/gif
Size: 105 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-dev/attachments/20180209/a5046b72/attachment.gif>