[cfe-dev] [llvm-dev] the as-if rule / perf vs. security

[David Chisnall via cfe-dev]

On 16 Mar 2016, at 18:50, Stephen Canon via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
>> 
>> On Mar 16, 2016, at 2:39 PM, Stephen Canon via cfe-dev <cfe-dev at lists.llvm.org> wrote:
>> 
>> Hypothesizing about architectures with larger-than-cacheline vectors, there’s also the possibility of changing externally observable behavior by loading a catchline-sized donut hole.
>> 
>> I believe that a very conservative set of criteria that nonetheless license this almost all the time is something like
>> 
>> 1. both ends of vector are used
>> 2. vector is smaller than a cacheline
> 
> As illustrated by David’s followup, this should really be “vector is smaller than than granularity of cache and memory protection on targeted architecture.”

Alignment should also be taken into account.  Consider the memory locations:

ABCDEFGH

If you have a vector ABCD and a vector EFGH, of which you access C and F, then you might consider creating a vector CDEF.  The vector is smaller than a cache line, but still may span a cache line boundary.  I’ve not looked at the latest generation, but with earlier AVX implementations an unaligned load or store could be a factor of around 30 slower than an aligned one.  You may end up with significantly slower code if you attempt to coalesce these two memory operations.

David