[cfe-dev] Data layout and clang

[JP]

Clang is generating load and stores with an alignment of 8 for my target 
even though I've set the datalayout and everything else I can think of 
to 32 bit alignment.  Any idea as to what I'm doing wrong?

The problematic line is:
   store i64 %x, i64* %x.addr, align 8

There's also the discrepancy between the alloca alignment of 4 and the 
store alignment of 8.

In Targets.cpp I've set:
     LongLongWidth = 64;
     LongLongAlign = 32;
     DoubleWidth = 64;
     DoubleAlign = 32;
     LongDoubleWidth = 64;
     LongDoubleAlign = 32;
     DescriptionString = 
"E-p:32:32:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-a64:32:32-S32-s64:32:32-n32";


Relevant parts from the C file:

void t3 (long long x)
{
   if (x != 0x80000fffULL)
     abort ();
}

Relevant parts from the IR file:

target datalayout = 
"E-p:32:32:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-a64:32:32-S32-s64:32:32-n32"

define void @t3(i64 %x) nounwind {
entry:
   %x.addr = alloca i64, align 4
   store i64 %x, i64* %x.addr, align 8
   call void @llvm.dbg.declare(metadata !{i64* %x.addr}, metadata !42), 
!dbg !43
   %0 = load i64* %x.addr, align 8, !dbg !44
   %cmp = icmp ne i64 %0, 2147487743, !dbg !44
   br i1 %cmp, label %if.then, label %if.end, !dbg !44

if.then:                                          ; preds = %entry
   call void @abort() noreturn, !dbg !46
   unreachable, !dbg !46

if.end:                                           ; preds = %entry
   ret void, !dbg !47
}