[clang] [X86] Allow PSHUFD/PSHUFLW/PSHUFW intrinsics in constexpr. (PR #161210)
Simon Pilgrim via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 2 02:53:45 PDT 2025
================
@@ -2773,6 +2773,62 @@ static bool interp__builtin_blend(InterpState &S, CodePtr OpPC,
return true;
}
+enum class Half { None, Low, High };
+
+static bool interp__builtin_ia32_pshuf(InterpState &S, CodePtr OpPC,
+ const CallExpr *Call, Half whichHalf) {
+ assert(Call->getNumArgs() == 2 && "masked forms handled via select*");
+ APSInt ControlImm = popToAPSInt(S, Call->getArg(1));
+ const Pointer &Src = S.Stk.pop<Pointer>();
+ const Pointer &Dst = S.Stk.peek<Pointer>();
+
+ unsigned NumElems = Dst.getNumElems();
+ PrimType ElemT = Dst.getFieldDesc()->getPrimType();
+
+ unsigned ElemBits = static_cast<unsigned>(primSize(ElemT) * 8);
+ if (ElemBits != 16 && ElemBits != 32)
+ return false;
+
+ unsigned LaneElts = 128u / ElemBits;
+ assert(LaneElts && (NumElems % LaneElts == 0));
+
+ uint8_t ctl = static_cast<uint8_t>(ControlImm.getZExtValue());
+
+ for (unsigned idx = 0; idx != NumElems; idx++) {
+ unsigned LaneBase = (idx / LaneElts) * LaneElts;
+ unsigned LaneIdx = idx % LaneElts;
+
+ unsigned SrcIdx = idx;
+
+ if (ElemBits == 32) {
+ unsigned sel = (ctl >> (2 * LaneIdx)) & 0x3;
----------------
RKSimon wrote:
common expression - hoist this: `unsigned Sel = (Ctrl >> (2 * LaneIdx)) & 0x3;` and then adjust it for the ShufHW case
https://github.com/llvm/llvm-project/pull/161210
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