[clang] [CIR] Upstream `AddressSpace` support for `PointerType` (PR #161028)

[David Rivera via cfe-commits]

================
@@ -297,6 +317,20 @@ bool RecordType::isLayoutIdentical(const RecordType &other) {
 // Data Layout information for types
 //===----------------------------------------------------------------------===//
 
+llvm::TypeSize
+PointerType::getTypeSizeInBits(const ::mlir::DataLayout &dataLayout,
+                               ::mlir::DataLayoutEntryListRef params) const {
+  // FIXME: improve this in face of address spaces
----------------
RiverDave wrote:

Took a look in OG:

- every major target derived from `TargetInfo/TransferableTarget` seems to implement their respective pointer getters based on target/addr space eg:

X86.h

```cpp
uint64_t getPointerWidthV(LangAS AS) const override {
  unsigned TargetAddrSpace = getTargetAddressSpace(AS);
  if (TargetAddrSpace == ptr32_sptr || TargetAddrSpace == ptr32_uptr)
    return 32;  // 32-bit pointers for specific address spaces
  if (TargetAddrSpace == ptr64)
    return 64;  // 64-bit pointers for ptr64 address space
  return PointerWidth;  // Default width
}
```

AMDGPU.h

```cpp
uint64_t getPointerWidthV(LangAS AS) const override {
  if (isR600(getTriple()))
    return 32;  // R600 always uses 32-bit pointers
  unsigned TargetAS = getTargetAddressSpace(AS);
  
  if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS ||
      TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS)
    return 32;  // Private/Local use 32-bit pointers
  
  return 64;  // Global/Constant use 64-bit pointers
}
```

Did a pretty shallow look but all of our target specific stuff seems to be within ABIIInfo which is initialized based on the CIRGen TargetInfo:

```cpp
class X8664TargetCIRGenInfo : public TargetCIRGenInfo {
public:
  X8664TargetCIRGenInfo(CIRGenTypes &cgt)
      : TargetCIRGenInfo(std::make_unique<X8664ABIInfo>(cgt)) {}
};

} // namespace

std::unique_ptr<TargetCIRGenInfo>
clang::CIRGen::createX8664TargetCIRGenInfo(CIRGenTypes &cgt) {
  return std::make_unique<X8664TargetCIRGenInfo>(cgt);
}

```

I guess we I could track this missing feature in the already existing:

  `static bool cirgenABIInfo() { return false; }`

https://github.com/llvm/llvm-project/pull/161028