[clang] [llvm] [NVPTX] Change the alloca address space in NVPTXLowerAlloca (PR #154814)

[Theodoros Theodoridis via cfe-commits]

================
@@ -1444,15 +1444,16 @@ void clang::emitBackendOutput(CompilerInstance &CI, CodeGenOptions &CGOpts,
 
   // Verify clang's TargetInfo DataLayout against the LLVM TargetMachine's
   // DataLayout.
-  if (AsmHelper.TM) {
-    std::string DLDesc = M->getDataLayout().getStringRepresentation();
-    if (DLDesc != TDesc) {
+  if (AsmHelper.TM)
+    if (!AsmHelper.TM->isCompatibleDataLayout(M->getDataLayout()) ||
+        !AsmHelper.TM->isCompatibleDataLayout(DataLayout(TDesc))) {
+      std::string DLDesc = M->getDataLayout().getStringRepresentation();
----------------
thetheodor wrote:

A lot (most?) of these address space casts in the tests stem from front-end lowering patterns like this:
```
define hidden noundef i32 @_Z3fooRi(ptr noundef nonnull align 4 dereferenceable(4) %a) #3 {
entry:
  %retval = alloca i32, align 4, addrspace(5)
  %a.addr = alloca ptr, align 8, addrspace(5)
  %retval.ascast = addrspacecast ptr addrspace(5) %retval to ptr
  %a.addr.ascast = addrspacecast ptr addrspace(5) %a.addr to ptr
  store ptr %a, ptr %a.addr.ascast, align 8, !tbaa !12
  %0 = load ptr, ptr %a.addr.ascast, align 8, !tbaa !12, !nonnull !14, !align !15
  %1 = load i32, ptr %0, align 4, !tbaa !10
  ret i32 %1
}
```
and because no optimizations are enabled in these OpenMP tests, these alloca-cast-store-load chains are not simplified. Running SROA eliminates the noise:
```
; *** IR Dump After SROAPass on _Z3fooRi ***
; Function Attrs: convergent mustprogress nounwind
define hidden noundef i32 @_Z3fooRi(ptr noundef nonnull align 4 dereferenceable(4) %a) #3 {
entry:
  %0 = load i32, ptr %a, align 4, !tbaa !10
  ret i32 %0
}
```
The only casts not removed by SROA are for the OpenMP API calls that need generic addresses.

(The amdgpu OpenMP tests also include this pattern)


https://github.com/llvm/llvm-project/pull/154814