[PATCH] D56811: [Mem2Reg] Enable promotion for bitcastable load/store values

[Sergey Dmitriev via Phabricator via cfe-commits]

sdmitriev created this revision.
sdmitriev added a reviewer: andrew.w.kaylor.
Herald added subscribers: cfe-commits, javed.absar.

This patch enables Mem2Reg to handle loads/stores from/to bitcasted alloca
values as long as the loaded/stored value is bitcastable to the allocated
type (see example below). Such instruction sequences can be introduced by
the InstCombine pass as part of the load canonicalization.

    
  %f = alloca float, align 4
  ...
  %0 = getelementptr inbounds float, float* %A, i64 %idx
  %1 = bitcast float* %0 to i32*
  %2 = load i32, i32* %1, align 4
  %3 = bitcast float* %f to i32*
  store i32 %2, i32* %3, align 4


Repository:
  rC Clang

https://reviews.llvm.org/D56811

Files:
  test/CodeGen/aarch64-neon-vget.c
  test/CodeGen/arm_neon_intrinsics.c

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