[PATCH] D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed

[Mikhail Maltsev via Phabricator via cfe-commits]

miyuki created this revision.
miyuki added reviewers: eli.friedman, olista01, SjoerdMeijer.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

On targets that do not support FP16 natively LLVM currently legalizes
vectors of FP16 values by scalarizing them and promoting to FP32. This
causes problems for the following code:

  void foo(int, ...);
  
  typedef __attribute__((neon_vector_type(4))) __fp16 float16x4_t;
  void bar(float16x4_t x) {
    foo(42, x);
  }

According to the AAPCS (appendix A.2) float16x4_t is a containerized
vector fundamental type, so 'foo' expects that the 4 16-bit FP values
are packed into 2 32-bit registers, but instead bar promotes them to
4 single precision values.

Since we already handle scalar FP16 values in the frontend by
bitcasting them to/from integers, this patch adds similar handling for
vector types.

One existing test required some adjustments because we now generate
more bitcasts (so the patch changes the test to target a machine with
native FP16 support).


https://reviews.llvm.org/D50507

Files:
  lib/CodeGen/TargetInfo.cpp
  test/CodeGen/arm-vfp16-arguments.c
  test/CodeGen/arm_neon_intrinsics.c

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