r336637 - [X86] Use masked the masked scalar fma builtins to implement the default rounding version of the fma intrinsics.
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Mon Jul 9 21:38:29 PDT 2018
Author: ctopper
Date: Mon Jul 9 21:38:29 2018
New Revision: 336637
URL: http://llvm.org/viewvc/llvm-project?rev=336637&view=rev
Log:
[X86] Use masked the masked scalar fma builtins to implement the default rounding version of the fma intrinsics.
The rounding mode is checked in CGBuiltin.cpp to generate the correct intrinsic call.
Making this switch switchs the masking to use the i8 bitcast to <8 x i1> and extract i1 version of the IR for the mask. Previously we ended up with a scalar 'and' plus an icmp.
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/test/CodeGen/avx512f-builtins.c
Modified: cfe/trunk/lib/Headers/avx512fintrin.h
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=336637&r1=336636&r2=336637&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/avx512fintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512fintrin.h Mon Jul 9 21:38:29 2018
@@ -7770,11 +7770,11 @@ _mm512_maskz_getexp_ps (__mmask16 __U, _
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask_fmadd_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- (__v4sf) __A,
- (__v4sf) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddss3_mask((__v4sf)__W,
+ (__v4sf)__A,
+ (__v4sf)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fmadd_round_ss(A, B, C, R) \
@@ -7792,11 +7792,11 @@ _mm_mask_fmadd_ss (__m128 __W, __mmask8
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_maskz_fmadd_ss (__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __A,
- (__v4sf) __B,
- (__v4sf) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddss3_maskz((__v4sf)__A,
+ (__v4sf)__B,
+ (__v4sf)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fmadd_round_ss(U, A, B, C, R) \
@@ -7808,11 +7808,11 @@ _mm_maskz_fmadd_ss (__mmask8 __U, __m128
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask3_fmadd_ss (__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- (__v4sf) __X,
- (__v4sf) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmaddss3_mask3((__v4sf)__W,
+ (__v4sf)__X,
+ (__v4sf)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fmadd_round_ss(W, X, Y, U, R) \
@@ -7824,11 +7824,11 @@ _mm_mask3_fmadd_ss (__m128 __W, __m128 _
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask_fmsub_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- (__v4sf) __A,
- -(__v4sf) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddss3_mask((__v4sf)__W,
+ (__v4sf)__A,
+ -(__v4sf)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fmsub_round_ss(A, B, C, R) \
@@ -7846,11 +7846,11 @@ _mm_mask_fmsub_ss (__m128 __W, __mmask8
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_maskz_fmsub_ss (__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __A,
- (__v4sf) __B,
- -(__v4sf) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddss3_maskz((__v4sf)__A,
+ (__v4sf)__B,
+ -(__v4sf)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fmsub_round_ss(U, A, B, C, R) \
@@ -7862,11 +7862,11 @@ _mm_maskz_fmsub_ss (__mmask8 __U, __m128
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask3_fmsub_ss (__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- (__v4sf) __X,
- -(__v4sf) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmsubss3_mask3((__v4sf)__W,
+ (__v4sf)__X,
+ (__v4sf)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fmsub_round_ss(W, X, Y, U, R) \
@@ -7878,11 +7878,11 @@ _mm_mask3_fmsub_ss (__m128 __W, __m128 _
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask_fnmadd_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- -(__v4sf) __A,
- (__v4sf) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddss3_mask((__v4sf)__W,
+ -(__v4sf)__A,
+ (__v4sf)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fnmadd_round_ss(A, B, C, R) \
@@ -7900,11 +7900,11 @@ _mm_mask_fnmadd_ss (__m128 __W, __mmask8
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_maskz_fnmadd_ss (__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __A,
- -(__v4sf) __B,
- (__v4sf) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddss3_maskz((__v4sf)__A,
+ -(__v4sf)__B,
+ (__v4sf)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fnmadd_round_ss(U, A, B, C, R) \
@@ -7916,11 +7916,11 @@ _mm_maskz_fnmadd_ss (__mmask8 __U, __m12
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask3_fnmadd_ss (__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- -(__v4sf) __X,
- (__v4sf) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmaddss3_mask3((__v4sf)__W,
+ -(__v4sf)__X,
+ (__v4sf)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fnmadd_round_ss(W, X, Y, U, R) \
@@ -7932,11 +7932,11 @@ _mm_mask3_fnmadd_ss (__m128 __W, __m128
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask_fnmsub_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- -(__v4sf) __A,
- -(__v4sf) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddss3_mask((__v4sf)__W,
+ -(__v4sf)__A,
+ -(__v4sf)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fnmsub_round_ss(A, B, C, R) \
@@ -7954,11 +7954,11 @@ _mm_mask_fnmsub_ss (__m128 __W, __mmask8
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_maskz_fnmsub_ss (__mmask8 __U, __m128 __A, __m128 __B, __m128 __C)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __A,
- -(__v4sf) __B,
- -(__v4sf) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddss3_maskz((__v4sf)__A,
+ -(__v4sf)__B,
+ -(__v4sf)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fnmsub_round_ss(U, A, B, C, R) \
@@ -7970,11 +7970,11 @@ _mm_maskz_fnmsub_ss (__mmask8 __U, __m12
static __inline__ __m128 __DEFAULT_FN_ATTRS128
_mm_mask3_fnmsub_ss (__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U)
{
- __m128 __Z = __builtin_ia32_vfmaddss3((__v4sf) __W,
- -(__v4sf) __X,
- -(__v4sf) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmsubss3_mask3((__v4sf)__W,
+ -(__v4sf)__X,
+ (__v4sf)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fnmsub_round_ss(W, X, Y, U, R) \
@@ -7986,11 +7986,11 @@ _mm_mask3_fnmsub_ss (__m128 __W, __m128
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_fmadd_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- (__v2df) __A,
- (__v2df) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddsd3_mask((__v2df)__W,
+ (__v2df)__A,
+ (__v2df)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fmadd_round_sd(A, B, C, R) \
@@ -8008,11 +8008,11 @@ _mm_mask_fmadd_sd (__m128d __W, __mmask8
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_fmadd_sd (__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __A,
- (__v2df) __B,
- (__v2df) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddsd3_maskz((__v2df)__A,
+ (__v2df)__B,
+ (__v2df)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fmadd_round_sd(U, A, B, C, R) \
@@ -8024,11 +8024,11 @@ _mm_maskz_fmadd_sd (__mmask8 __U, __m128
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask3_fmadd_sd (__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- (__v2df) __X,
- (__v2df) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmaddsd3_mask3((__v2df)__W,
+ (__v2df)__X,
+ (__v2df)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fmadd_round_sd(W, X, Y, U, R) \
@@ -8040,11 +8040,11 @@ _mm_mask3_fmadd_sd (__m128d __W, __m128d
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_fmsub_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- (__v2df) __A,
- -(__v2df) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddsd3_mask((__v2df)__W,
+ (__v2df)__A,
+ -(__v2df)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fmsub_round_sd(A, B, C, R) \
@@ -8062,11 +8062,11 @@ _mm_mask_fmsub_sd (__m128d __W, __mmask8
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_fmsub_sd (__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __A,
- (__v2df) __B,
- -(__v2df) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddsd3_maskz((__v2df)__A,
+ (__v2df)__B,
+ -(__v2df)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fmsub_round_sd(U, A, B, C, R) \
@@ -8078,11 +8078,11 @@ _mm_maskz_fmsub_sd (__mmask8 __U, __m128
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask3_fmsub_sd (__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- (__v2df) __X,
- -(__v2df) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmsubsd3_mask3((__v2df)__W,
+ (__v2df)__X,
+ (__v2df)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fmsub_round_sd(W, X, Y, U, R) \
@@ -8094,11 +8094,11 @@ _mm_mask3_fmsub_sd (__m128d __W, __m128d
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_fnmadd_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- -(__v2df) __A,
- (__v2df) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddsd3_mask((__v2df)__W,
+ -(__v2df)__A,
+ (__v2df)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fnmadd_round_sd(A, B, C, R) \
@@ -8116,11 +8116,11 @@ _mm_mask_fnmadd_sd (__m128d __W, __mmask
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_fnmadd_sd (__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __A,
- -(__v2df) __B,
- (__v2df) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddsd3_maskz((__v2df)__A,
+ -(__v2df)__B,
+ (__v2df)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fnmadd_round_sd(U, A, B, C, R) \
@@ -8132,11 +8132,11 @@ _mm_maskz_fnmadd_sd (__mmask8 __U, __m12
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask3_fnmadd_sd (__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- -(__v2df) __X,
- (__v2df) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmaddsd3_mask3((__v2df)__W,
+ -(__v2df)__X,
+ (__v2df)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fnmadd_round_sd(W, X, Y, U, R) \
@@ -8148,11 +8148,11 @@ _mm_mask3_fnmadd_sd (__m128d __W, __m128
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask_fnmsub_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- -(__v2df) __A,
- -(__v2df) __B);
- __W[0] = (__U & 1) ? __Z[0] : __W[0];
- return __W;
+ return __builtin_ia32_vfmaddsd3_mask((__v2df)__W,
+ -(__v2df)__A,
+ -(__v2df)__B,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_fnmsub_round_sd(A, B, C, R) \
@@ -8170,11 +8170,11 @@ _mm_mask_fnmsub_sd (__m128d __W, __mmask
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_maskz_fnmsub_sd (__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __A,
- -(__v2df) __B,
- -(__v2df) __C);
- __A[0] = (__U & 1) ? __Z[0] : 0;
- return __A;
+ return __builtin_ia32_vfmaddsd3_maskz((__v2df)__A,
+ -(__v2df)__B,
+ -(__v2df)__C,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_maskz_fnmsub_round_sd(U, A, B, C, R) \
@@ -8187,11 +8187,11 @@ _mm_maskz_fnmsub_sd (__mmask8 __U, __m12
static __inline__ __m128d __DEFAULT_FN_ATTRS128
_mm_mask3_fnmsub_sd (__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U)
{
- __m128d __Z = __builtin_ia32_vfmaddsd3((__v2df) __W,
- -(__v2df) __X,
- -(__v2df) __Y);
- __Y[0] = (__U & 1) ? __Z[0] : __Y[0];
- return __Y;
+ return __builtin_ia32_vfmsubsd3_mask3((__v2df)__W,
+ -(__v2df)__X,
+ (__v2df)__Y,
+ (__mmask8)__U,
+ _MM_FROUND_CUR_DIRECTION);
}
#define _mm_mask3_fnmsub_round_sd(W, X, Y, U, R) \
Modified: cfe/trunk/test/CodeGen/avx512f-builtins.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512f-builtins.c?rev=336637&r1=336636&r2=336637&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/avx512f-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx512f-builtins.c Mon Jul 9 21:38:29 2018
@@ -7235,24 +7235,14 @@ __m128 test_mm_maskz_getmant_round_ss(__
__m128 test_mm_mask_fmadd_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){
// CHECK-LABEL: @test_mm_mask_fmadd_ss
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[A]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_mask_fmadd_ss(__W, __U, __A, __B);
}
@@ -7281,23 +7271,14 @@ __m128 test_mm_mask_fmadd_round_ss(__m12
__m128 test_mm_maskz_fmadd_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){
// CHECK-LABEL: @test_mm_maskz_fmadd_ss
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float 0.000000e+00
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_maskz_fmadd_ss(__U, __A, __B, __C);
}
@@ -7316,24 +7297,14 @@ __m128 test_mm_maskz_fmadd_round_ss(__mm
__m128 test_mm_mask3_fmadd_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fmadd_ss
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[ORIGC:%.+]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[C]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGC]], float [[SEL]], i64 0
return _mm_mask3_fmadd_ss(__W, __X, __Y, __U);
}
@@ -7352,25 +7323,15 @@ __m128 test_mm_mask3_fmadd_round_ss(__m1
__m128 test_mm_mask_fmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){
// CHECK-LABEL: @test_mm_mask_fmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[A]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_mask_fmsub_ss(__W, __U, __A, __B);
}
@@ -7401,24 +7362,15 @@ __m128 test_mm_mask_fmsub_round_ss(__m12
__m128 test_mm_maskz_fmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){
// CHECK-LABEL: @test_mm_maskz_fmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float 0.000000e+00
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_maskz_fmsub_ss(__U, __A, __B, __C);
}
@@ -7438,25 +7390,16 @@ __m128 test_mm_maskz_fmsub_round_ss(__mm
__m128 test_mm_mask3_fmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[ORIGC:%.+]]
+ // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: [[C2:%.+]] = extractelement <4 x float> [[ORIGC]], i64 0
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[C2]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGC]], float [[SEL]], i64 0
return _mm_mask3_fmsub_ss(__W, __X, __Y, __U);
}
@@ -7477,25 +7420,15 @@ __m128 test_mm_mask3_fmsub_round_ss(__m1
__m128 test_mm_mask_fnmadd_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){
// CHECK-LABEL: @test_mm_mask_fnmadd_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[A]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_mask_fnmadd_ss(__W, __U, __A, __B);
}
@@ -7526,24 +7459,15 @@ __m128 test_mm_mask_fnmadd_round_ss(__m1
__m128 test_mm_maskz_fnmadd_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){
// CHECK-LABEL: @test_mm_maskz_fnmadd_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float 0.000000e+00
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_maskz_fnmadd_ss(__U, __A, __B, __C);
}
@@ -7563,25 +7487,15 @@ __m128 test_mm_maskz_fnmadd_round_ss(__m
__m128 test_mm_mask3_fnmadd_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fnmadd_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[ORIGC:%.+]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[C]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGC]], float [[SEL]], i64 0
return _mm_mask3_fnmadd_ss(__W, __X, __Y, __U);
}
@@ -7601,26 +7515,16 @@ __m128 test_mm_mask3_fnmadd_round_ss(__m
__m128 test_mm_mask_fnmsub_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B){
// CHECK-LABEL: @test_mm_mask_fnmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[A]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_mask_fnmsub_ss(__W, __U, __A, __B);
}
@@ -7653,25 +7557,16 @@ __m128 test_mm_mask_fnmsub_round_ss(__m1
__m128 test_mm_maskz_fnmsub_ss(__mmask8 __U, __m128 __A, __m128 __B, __m128 __C){
// CHECK-LABEL: @test_mm_maskz_fnmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <4 x float> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float 0.000000e+00
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGA]], float [[SEL]], i64 0
return _mm_maskz_fnmsub_ss(__U, __A, __B, __C);
}
@@ -7692,26 +7587,17 @@ __m128 test_mm_maskz_fnmsub_round_ss(__m
__m128 test_mm_mask3_fnmsub_ss(__m128 __W, __m128 __X, __m128 __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fnmsub_ss
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: extractelement <4 x float> %{{.*}}, i64 0
- // CHECK: call float @llvm.fma.f32(float %{{.*}}, float %{{.*}}, float %{{.*}})
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <4 x float> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi float
- // CHECK: insertelement <4 x float> %{{.*}}, float %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, [[ORIGC:%.+]]
+ // CHECK: [[A:%.+]] = extractelement <4 x float> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <4 x float> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <4 x float> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call float @llvm.fma.f32(float [[A]], float [[B]], float [[C]])
+ // CHECK-NEXT: [[C2:%.+]] = extractelement <4 x float> [[ORIGC]], i64 0
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, float [[FMA]], float [[C2]]
+ // CHECK-NEXT: insertelement <4 x float> [[ORIGC]], float [[SEL]], i64 0
return _mm_mask3_fnmsub_ss(__W, __X, __Y, __U);
}
@@ -7733,24 +7619,14 @@ __m128 test_mm_mask3_fnmsub_round_ss(__m
__m128d test_mm_mask_fmadd_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){
// CHECK-LABEL: @test_mm_mask_fmadd_sd
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[A]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_mask_fmadd_sd(__W, __U, __A, __B);
}
@@ -7779,23 +7655,14 @@ __m128d test_mm_mask_fmadd_round_sd(__m1
__m128d test_mm_maskz_fmadd_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){
// CHECK-LABEL: @test_mm_maskz_fmadd_sd
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double 0.000000e+00
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_maskz_fmadd_sd(__U, __A, __B, __C);
}
@@ -7814,24 +7681,14 @@ __m128d test_mm_maskz_fmadd_round_sd(__m
__m128d test_mm_mask3_fmadd_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fmadd_sd
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[ORIGC:%.+]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[C]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGC]], double [[SEL]], i64 0
return _mm_mask3_fmadd_sd(__W, __X, __Y, __U);
}
@@ -7850,25 +7707,15 @@ __m128d test_mm_mask3_fmadd_round_sd(__m
__m128d test_mm_mask_fmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){
// CHECK-LABEL: @test_mm_mask_fmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[A]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_mask_fmsub_sd(__W, __U, __A, __B);
}
@@ -7899,24 +7746,15 @@ __m128d test_mm_mask_fmsub_round_sd(__m1
__m128d test_mm_maskz_fmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){
// CHECK-LABEL: @test_mm_maskz_fmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double 0.000000e+00
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_maskz_fmsub_sd(__U, __A, __B, __C);
}
@@ -7936,25 +7774,16 @@ __m128d test_mm_maskz_fmsub_round_sd(__m
__m128d test_mm_mask3_fmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, [[ORIGC:%.+]]
+ // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: [[C2:%.+]] = extractelement <2 x double> [[ORIGC]], i64 0
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[C2]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGC]], double [[SEL]], i64 0
return _mm_mask3_fmsub_sd(__W, __X, __Y, __U);
}
@@ -7975,25 +7804,15 @@ __m128d test_mm_mask3_fmsub_round_sd(__m
__m128d test_mm_mask_fnmadd_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){
// CHECK-LABEL: @test_mm_mask_fnmadd_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[A]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_mask_fnmadd_sd(__W, __U, __A, __B);
}
@@ -8024,24 +7843,15 @@ __m128d test_mm_mask_fnmadd_round_sd(__m
__m128d test_mm_maskz_fnmadd_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){
// CHECK-LABEL: @test_mm_maskz_fnmadd_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.+]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double 0.000000e+00
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_maskz_fnmadd_sd(__U, __A, __B, __C);
}
@@ -8061,25 +7871,15 @@ __m128d test_mm_maskz_fnmadd_round_sd(__
__m128d test_mm_mask3_fnmadd_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fnmadd_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[ORIGC:%.+]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[C]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGC]], double [[SEL]], i64 0
return _mm_mask3_fnmadd_sd(__W, __X, __Y, __U);
}
@@ -8099,26 +7899,16 @@ __m128d test_mm_mask3_fnmadd_round_sd(__
__m128d test_mm_mask_fnmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B){
// CHECK-LABEL: @test_mm_mask_fnmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[A]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_mask_fnmsub_sd(__W, __U, __A, __B);
}
@@ -8151,25 +7941,16 @@ __m128d test_mm_mask_fnmsub_round_sd(__m
__m128d test_mm_maskz_fnmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C){
// CHECK-LABEL: @test_mm_maskz_fnmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[A:%.+]] = extractelement <2 x double> [[ORIGA:%.]], i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double 0.000000e+00
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGA]], double [[SEL]], i64 0
return _mm_maskz_fnmsub_sd(__U, __A, __B, __C);
}
@@ -8190,26 +7971,17 @@ __m128d test_mm_maskz_fnmsub_round_sd(__
__m128d test_mm_mask3_fnmsub_sd(__m128d __W, __m128d __X, __m128d __Y, __mmask8 __U){
// CHECK-LABEL: @test_mm_mask3_fnmsub_sd
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: extractelement <2 x double> %{{.*}}, i64 0
- // CHECK: call double @llvm.fma.f64(double %{{.*}}, double %{{.*}}, double %{{.*}})
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i64 0
- // CHECK: zext i8 %{{.*}} to i32
- // CHECK: and i32 %{{.*}}, 1
- // CHECK: icmp ne i32 %{{.*}}, 0
- // CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: extractelement <2 x double> %{{.*}}, i32 0
- // CHECK: br label %{{.*}}
-
- // CHECK: phi double
- // CHECK: insertelement <2 x double> %{{.*}}, double %{{.*}}, i32 0
+ // CHECK: [[NEG:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{.*}}
+ // CHECK: [[NEG2:%.+]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, [[ORIGC:%.+]]
+ // CHECK: [[A:%.+]] = extractelement <2 x double> %{{.*}}, i64 0
+ // CHECK-NEXT: [[B:%.+]] = extractelement <2 x double> [[NEG]], i64 0
+ // CHECK-NEXT: [[C:%.+]] = extractelement <2 x double> [[NEG2]], i64 0
+ // CHECK-NEXT: [[FMA:%.+]] = call double @llvm.fma.f64(double [[A]], double [[B]], double [[C]])
+ // CHECK-NEXT: [[C2:%.+]] = extractelement <2 x double> [[ORIGC]], i64 0
+ // CHECK-NEXT: bitcast i8 %{{.*}} to <8 x i1>
+ // CHECK-NEXT: extractelement <8 x i1> %{{.*}}, i64 0
+ // CHECK-NEXT: [[SEL:%.+]] = select i1 %{{.*}}, double [[FMA]], double [[C2]]
+ // CHECK-NEXT: insertelement <2 x double> [[ORIGC]], double [[SEL]], i64 0
return _mm_mask3_fnmsub_sd(__W, __X, __Y, __U);
}
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