[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

[Reid Kleckner via Phabricator via cfe-commits]

rnk added subscribers: craig.topper, chandlerc.
rnk added a comment.

I read up a little bit on TSX and HLE:
https://software.intel.com/en-us/node/524022
https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions

These HLE variants of the usual atomic exchange intrinsics add the `xacquire` and `xrelease` prefixes. They use the same encoding as the `repe` and `repne` prefixes, which previously didn't do anything on Intel (and presumably) AMD hardware.

They are a hint to the processor that this is a short critical section, and it is likely that the entire critical section can be entered, run, and committed to memory before another thread needs to use the memory used by the critical section. Your implementation doesn't add these prefixes, but the code will execute correctly. This functionality relies on TSX, which it looks like Intel added some time in 2014, so it's probably widely available.

Personally, I don't want to implement these intrinsics this way. We've already implemented intrinsics "our way" instead of doing whatever Visual C does, and it just leads to developer confusion when they discover that the compiler didn't emit the instruction they want. For example, the rotate intrinsics often don't work (https://llvm.org/pr37387) and the bittestandset (bts) intrinsics are just broken (http://llvm.org/pr33188).

@chandlerc @craig.topper are there any plans for representing HLE hints on atomic instructions in LLVM IR? Alternatively, do you know who would be most interested in adding them? This seems like a reasonable place to use metadata or SubclassOptionalData on regular `atomicrmw` instructions, since it's a hint that could be dropped. As far as mid-level passes are concerned, these are vanilla acquire and release instructions.


Repository:
  rC Clang

https://reviews.llvm.org/D47672