[PATCH] D42811: [CodeGen][va_args] Correct Vector Struct va-arg 'in_reg' code gen

[Erich Keane via Phabricator via cfe-commits]

erichkeane created this revision.
erichkeane added reviewers: rsmith, rjmccall.

When trying to track down a different bug, we discovered
that calling `__builtin_va_arg` on a vec3f type caused
the SROA pass to issue a warning that there was an illegal
access.

Further research showed that the vec3f type is
alloca'ed as size '12', but the `_builtin_va_arg` code
on x86_64 was always loading this out of registers as 
{double, double}. Thus, the 2nd store into the vec3f
was storing in bytes 12-15!

This patch alters the original implementation which always
assumed {double, double} to use the actual coerced type 
instead, so the LLVM-IR generated is a load/GEP/store of
a <2 x float> and a float, rather than a double and a double.

Tests were added for all combinations I could think of that
would fit in 2 FP registers, and all work exactly as expected.


Repository:
  rC Clang

https://reviews.llvm.org/D42811

Files:
  lib/CodeGen/TargetInfo.cpp
  test/CodeGen/x86_64-floatvectors.c

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