r322562 - [SystemZ] Support vector registers with inline asm

[Ulrich Weigand via cfe-commits]

Author: uweigand
Date: Tue Jan 16 07:39:23 2018
New Revision: 322562

URL: http://llvm.org/viewvc/llvm-project?rev=322562&view=rev
Log:
[SystemZ] Support vector registers with inline asm

Allow using vector register names and the "v" constraint
in inline asm to ensure compatibility with GCC.


Modified:
    cfe/trunk/lib/Basic/Targets/SystemZ.cpp
    cfe/trunk/lib/Basic/Targets/SystemZ.h

Modified: cfe/trunk/lib/Basic/Targets/SystemZ.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/SystemZ.cpp?rev=322562&r1=322561&r2=322562&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets/SystemZ.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/SystemZ.cpp Tue Jan 16 07:39:23 2018
@@ -30,15 +30,30 @@ const Builtin::Info SystemZTargetInfo::B
 };
 
 const char *const SystemZTargetInfo::GCCRegNames[] = {
-    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6", "r7",  "r8",  "r9", "r10",
-    "r11", "r12", "r13", "r14", "r15", "f0",  "f2", "f4",  "f6",  "f1", "f3",
-    "f5",  "f7",  "f8",  "f10", "f12", "f14", "f9", "f11", "f13", "f15"
+    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
+    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
+    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
+    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15",
+    /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0",  "a1",
+    "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
+    "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
+};
+
+const TargetInfo::AddlRegName GCCAddlRegNames[] = {
+    {{"v0"}, 16}, {{"v2"},  17}, {{"v4"},  18}, {{"v6"},  19},
+    {{"v1"}, 20}, {{"v3"},  21}, {{"v5"},  22}, {{"v7"},  23},
+    {{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27},
+    {{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31}
 };
 
 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
   return llvm::makeArrayRef(GCCRegNames);
 }
 
+ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
+  return llvm::makeArrayRef(GCCAddlRegNames);
+}
+
 bool SystemZTargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   switch (*Name) {
@@ -48,6 +63,7 @@ bool SystemZTargetInfo::validateAsmConst
   case 'a': // Address register
   case 'd': // Data register (equivalent to 'r')
   case 'f': // Floating-point register
+  case 'v': // Vector register
     Info.setAllowsRegister();
     return true;
 

Modified: cfe/trunk/lib/Basic/Targets/SystemZ.h
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/SystemZ.h?rev=322562&r1=322561&r2=322562&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets/SystemZ.h (original)
+++ cfe/trunk/lib/Basic/Targets/SystemZ.h Tue Jan 16 07:39:23 2018
@@ -62,6 +62,8 @@ public:
     return None;
   }
 
+  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
+
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &info) const override;