r322514 - [RISCV] Fix test failures on non-assert builds introduced in r322494

[Alex Bradbury via cfe-commits]

Author: asb
Date: Mon Jan 15 12:45:15 2018
New Revision: 322514

URL: http://llvm.org/viewvc/llvm-project?rev=322514&view=rev
Log:
[RISCV] Fix test failures on non-assert builds introduced in r322494

Thanks to Eli Friedman, who suggested the reason these tests failed on a few 
buildbots yet works fine locally is because non-assert builds don't emit value 
labels.

Modified:
    cfe/trunk/test/CodeGen/riscv32-abi.c
    cfe/trunk/test/CodeGen/riscv64-abi.c

Modified: cfe/trunk/test/CodeGen/riscv32-abi.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/riscv32-abi.c?rev=322514&r1=322513&r2=322514&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/riscv32-abi.c (original)
+++ cfe/trunk/test/CodeGen/riscv32-abi.c Mon Jan 15 12:45:15 2018
@@ -269,8 +269,7 @@ int f_va_1(char *fmt, ...) {
 // correct offsets are used.
 
 // CHECK-LABEL: @f_va_2(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 4
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[V:%.*]] = alloca double, align 8
 // CHECK-NEXT:    store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 4
@@ -303,8 +302,7 @@ double f_va_2(char *fmt, ...) {
 // Two "aligned" register pairs.
 
 // CHECK-LABEL: @f_va_3(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 4
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[V:%.*]] = alloca double, align 8
 // CHECK-NEXT:    [[W:%.*]] = alloca i32, align 4
@@ -357,8 +355,7 @@ double f_va_3(char *fmt, ...) {
 }
 
 // CHECK-LABEL: define i32 @f_va_4(i8* %fmt, ...) {{.*}} {
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 4
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 4
 // CHECK-NEXT:    [[V:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[LD:%.*]] = alloca fp128, align 16

Modified: cfe/trunk/test/CodeGen/riscv64-abi.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/riscv64-abi.c?rev=322514&r1=322513&r2=322514&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/riscv64-abi.c (original)
+++ cfe/trunk/test/CodeGen/riscv64-abi.c Mon Jan 15 12:45:15 2018
@@ -267,8 +267,7 @@ int f_va_1(char *fmt, ...) {
 // correct offsets are used.
 
 // CHECK-LABEL: @f_va_2(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 8
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[V:%.*]] = alloca fp128, align 16
 // CHECK-NEXT:    store i8* [[FMT:%.*]], i8** [[FMT_ADDR]], align 8
@@ -301,8 +300,7 @@ long double f_va_2(char *fmt, ...) {
 // Two "aligned" register pairs.
 
 // CHECK-LABEL: @f_va_3(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 8
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[V:%.*]] = alloca fp128, align 16
 // CHECK-NEXT:    [[W:%.*]] = alloca i32, align 4
@@ -355,8 +353,7 @@ long double f_va_3(char *fmt, ...) {
 }
 
 // CHECK-LABEL: @f_va_4(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[FMT_ADDR:%.*]] = alloca i8*, align 8
+// CHECK:         [[FMT_ADDR:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[VA:%.*]] = alloca i8*, align 8
 // CHECK-NEXT:    [[V:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[TS:%.*]] = alloca [[STRUCT_TINY:%.*]], align 2