[PATCH] D41516: emmintrin.h documentation fixes and updates

[Katya Romanova via Phabricator via cfe-commits]

kromanova added inline comments.
Herald added a subscriber: llvm-commits.


================
Comment at: cfe/trunk/lib/Headers/emmintrin.h:3865
 ///
-/// This intrinsic corresponds to the <c> VPUNPCKLQDQ / PUNPCKLQDQ </c>
-///   instruction.
+/// This intrinsic does not correspond to a specific instruction.
 ///
----------------
It's better if you use the same language as for many intrinsics "before" and "after". Just for consistency purpose.

```
/// This intrinsic is a utility function and does not correspond to a specific
///    instruction.


================
Comment at: cfe/trunk/lib/Headers/emmintrin.h:4683
 ///
-/// This intrinsic has no corresponding instruction.
+/// This intrinsic corresponds to the <c> MOVDQ2Q </c> instruction.
 ///
----------------
kromanova wrote:
> I'm not sure about this change.
> 
> Intel documentation says they generate MOVDQ2Q (don't have icc handy to try).
> However, I've tried on Linux/X86_64 with clang and gcc, - and we just return.
> 
Though I suspect it's possible to generate movdq2q, I couldn't come up with an test to trigger this instruction generation.
Should we revert this change?


```
__m64 fooepi64_pi64 (__m128i a, __m128 c)
{
  __m64 x;

  x = _mm_movepi64_pi64 (a);
  return x;
}

```

on Linux we generate return instruction. 
I would expect (v)movq %xmm0,%rax to be generated instead of retq. 
Am I missing something? Why do we return 64 bit integer in xmm register rather than in %rax?



================
Comment at: cfe/trunk/lib/Headers/emmintrin.h:4700
 ///
-/// This intrinsic corresponds to the <c> VMOVQ / MOVQ / MOVD </c> instruction.
+/// This intrinsic corresponds to the <c> MOVD+VMOVQ </c> instruction.
 ///
----------------
For Linux x86_64 I can only generate VMOVQ (or MOVQ) instructions respectively for AVX/non-AVX case.
Can we even generate MOVD+VMOVQ?
How we want to document this intrinsic?


I have a similar question as above.
```
__m128i foopi64_epi64 (__m64 a)
{
  __m128i x;

  x = _mm_movpi64_epi64 (a);
  return x;
}
```

Why we generate this code 
```
        vmovq   %xmm0, %rax
        vmovq   %rax, %xmm0
        retq
}
```
instead of something simple like vmovq %rdi, %xmm0? 





Repository:
  rL LLVM

https://reviews.llvm.org/D41516