[PATCH] D41523: xmmintrin.h documentation fixes and updates

[Katya Romanova via Phabricator via cfe-commits]

kromanova added inline comments.


================
Comment at: lib/Headers/xmmintrin.h:2199
 ///
-/// This intrinsic corresponds to the <c> VPINSRW / PINSRW </c> instruction.
+/// This intrinsic corresponds to the <c> PINSRW </c> instruction.
 ///
----------------
craig.topper wrote:
> Why is VPINSRW removed?
I suspect the rational is the same I talked about in mmintrin.h review. 
This intrinsic should use MMX registers and shouldn't have corresponding AVX instruction(s).

I've tried this and with or without -mavx for Linux/x86_64 we generate PINSRW in both cases (i.e. I wasn't able to trigger generation of VEX prefixed instruction).

__m64 foo (__m64 a, int b)
{
  __m64 x;
  x = _mm_insert_pi16 (a, b, 0);
  return x;
}



================
Comment at: lib/Headers/xmmintrin.h:2659
 ///
-/// This intrinsic corresponds to the <c> VMOVSS / MOVSS </c> instruction.
+/// This intrinsic corresponds to the <c> VBLENDPS / BLENDPS </c> instruction.
 ///
----------------
craig.topper wrote:
> MOVSS is correct for pre SSE4.1 targets.
That's correct.
Doug, I think we should write:
VBLENDPS / BLENDPS / MOVSS


https://reviews.llvm.org/D41523