r318234 - Simplify CpuIs code to use include from LLVM
Erich Keane via cfe-commits
cfe-commits at lists.llvm.org
Tue Nov 14 16:11:24 PST 2017
Author: erichkeane
Date: Tue Nov 14 16:11:24 2017
New Revision: 318234
URL: http://llvm.org/viewvc/llvm-project?rev=318234&view=rev
Log:
Simplify CpuIs code to use include from LLVM
LLVM exposes a file in the backend (X86TargetParser.def) that
contains information about the correct list of CpuIs values.
This patch removes 2 of the copied and pasted versions of this
list from clang and instead includes the data from the .def file.
Differential Revision: https://reviews.llvm.org/D40054
Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=318234&r1=318233&r2=318234&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Tue Nov 14 16:11:24 2017
@@ -1291,36 +1291,12 @@ bool X86TargetInfo::validateCpuSupports(
// rather than the full range of cpus.
bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
return llvm::StringSwitch<bool>(FeatureStr)
- .Case("amd", true)
- .Case("amdfam10h", true)
- .Case("amdfam15h", true)
- .Case("amdfam17h", true)
- .Case("atom", true)
- .Case("barcelona", true)
- .Case("bdver1", true)
- .Case("bdver2", true)
- .Case("bdver3", true)
- .Case("bdver4", true)
- .Case("bonnell", true)
- .Case("broadwell", true)
- .Case("btver1", true)
- .Case("btver2", true)
- .Case("core2", true)
- .Case("corei7", true)
- .Case("haswell", true)
- .Case("intel", true)
- .Case("istanbul", true)
- .Case("ivybridge", true)
- .Case("knl", true)
- .Case("nehalem", true)
- .Case("sandybridge", true)
- .Case("shanghai", true)
- .Case("silvermont", true)
- .Case("skylake", true)
- .Case("skylake-avx512", true)
- .Case("slm", true)
- .Case("westmere", true)
- .Case("znver1", true)
+#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
+#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
+ .Cases(STR, ALIAS, true)
+#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
+#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
+#include "llvm/Support/X86TargetParser.def"
.Default(false);
}
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=318234&r1=318233&r2=318234&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Tue Nov 14 16:11:24 2017
@@ -30,8 +30,9 @@
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
-#include "llvm/Support/ScopedPrinter.h"
#include "llvm/Support/ConvertUTF.h"
+#include "llvm/Support/ScopedPrinter.h"
+#include "llvm/Support/TargetParser.h"
#include <sstream>
using namespace clang;
@@ -4626,8 +4627,8 @@ static bool HasExtraNeonArgument(unsigne
case NEON::BI__builtin_neon_vsha1cq_u32:
case NEON::BI__builtin_neon_vsha1pq_u32:
case NEON::BI__builtin_neon_vsha1mq_u32:
- case ARM::BI_MoveToCoprocessor:
- case ARM::BI_MoveToCoprocessor2:
+ case clang::ARM::BI_MoveToCoprocessor:
+ case clang::ARM::BI_MoveToCoprocessor2:
return false;
}
return true;
@@ -7497,78 +7498,6 @@ Value *CodeGenFunction::EmitX86CpuIs(con
Value *CodeGenFunction::EmitX86CpuIs(StringRef CPUStr) {
- // This enum contains the vendor, type, and subtype enums from the
- // runtime library concatenated together. The _START labels mark
- // the start and are used to adjust the value into the correct
- // encoding space.
- enum X86CPUs {
- INTEL = 1,
- AMD,
- CPU_TYPE_START,
- INTEL_BONNELL,
- INTEL_CORE2,
- INTEL_COREI7,
- AMDFAM10H,
- AMDFAM15H,
- INTEL_SILVERMONT,
- INTEL_KNL,
- AMD_BTVER1,
- AMD_BTVER2,
- AMDFAM17H,
- CPU_SUBTYPE_START,
- INTEL_COREI7_NEHALEM,
- INTEL_COREI7_WESTMERE,
- INTEL_COREI7_SANDYBRIDGE,
- AMDFAM10H_BARCELONA,
- AMDFAM10H_SHANGHAI,
- AMDFAM10H_ISTANBUL,
- AMDFAM15H_BDVER1,
- AMDFAM15H_BDVER2,
- AMDFAM15H_BDVER3,
- AMDFAM15H_BDVER4,
- AMDFAM17H_ZNVER1,
- INTEL_COREI7_IVYBRIDGE,
- INTEL_COREI7_HASWELL,
- INTEL_COREI7_BROADWELL,
- INTEL_COREI7_SKYLAKE,
- INTEL_COREI7_SKYLAKE_AVX512,
- };
-
- X86CPUs CPU =
- StringSwitch<X86CPUs>(CPUStr)
- .Case("amd", AMD)
- .Case("amdfam10h", AMDFAM10H)
- .Case("amdfam10", AMDFAM10H)
- .Case("amdfam15h", AMDFAM15H)
- .Case("amdfam15", AMDFAM15H)
- .Case("amdfam17h", AMDFAM17H)
- .Case("atom", INTEL_BONNELL)
- .Case("barcelona", AMDFAM10H_BARCELONA)
- .Case("bdver1", AMDFAM15H_BDVER1)
- .Case("bdver2", AMDFAM15H_BDVER2)
- .Case("bdver3", AMDFAM15H_BDVER3)
- .Case("bdver4", AMDFAM15H_BDVER4)
- .Case("bonnell", INTEL_BONNELL)
- .Case("broadwell", INTEL_COREI7_BROADWELL)
- .Case("btver1", AMD_BTVER1)
- .Case("btver2", AMD_BTVER2)
- .Case("core2", INTEL_CORE2)
- .Case("corei7", INTEL_COREI7)
- .Case("haswell", INTEL_COREI7_HASWELL)
- .Case("intel", INTEL)
- .Case("istanbul", AMDFAM10H_ISTANBUL)
- .Case("ivybridge", INTEL_COREI7_IVYBRIDGE)
- .Case("knl", INTEL_KNL)
- .Case("nehalem", INTEL_COREI7_NEHALEM)
- .Case("sandybridge", INTEL_COREI7_SANDYBRIDGE)
- .Case("shanghai", AMDFAM10H_SHANGHAI)
- .Case("silvermont", INTEL_SILVERMONT)
- .Case("skylake", INTEL_COREI7_SKYLAKE)
- .Case("skylake-avx512", INTEL_COREI7_SKYLAKE_AVX512)
- .Case("slm", INTEL_SILVERMONT)
- .Case("westmere", INTEL_COREI7_WESTMERE)
- .Case("znver1", AMDFAM17H_ZNVER1);
-
llvm::Type *Int32Ty = Builder.getInt32Ty();
// Matching the struct layout from the compiler-rt/libgcc structure that is
@@ -7587,22 +7516,22 @@ Value *CodeGenFunction::EmitX86CpuIs(Str
// range. Also adjust the expected value.
unsigned Index;
unsigned Value;
- if (CPU > CPU_SUBTYPE_START) {
- Index = 2;
- Value = CPU - CPU_SUBTYPE_START;
- } else if (CPU > CPU_TYPE_START) {
- Index = 1;
- Value = CPU - CPU_TYPE_START;
- } else {
- Index = 0;
- Value = CPU;
- }
+ std::tie(Index, Value) = StringSwitch<std::pair<unsigned, unsigned>>(CPUStr)
+#define X86_VENDOR(ENUM, STRING) \
+ .Case(STRING, {0u, static_cast<unsigned>(llvm::X86::ENUM)})
+#define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
+ .Cases(STR, ALIAS, {1u, static_cast<unsigned>(llvm::X86::ENUM)})
+#define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) \
+ .Case(STR, {1u, static_cast<unsigned>(llvm::X86::ENUM)})
+#define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) \
+ .Case(STR, {2u, static_cast<unsigned>(llvm::X86::ENUM)})
+#include "llvm/Support/X86TargetParser.def"
+ .Default({0, 0});
+ assert(Value != 0 && "Invalid CPUStr passed to CpuIs");
// Grab the appropriate field from __cpu_model.
- llvm::Value *Idxs[] = {
- ConstantInt::get(Int32Ty, 0),
- ConstantInt::get(Int32Ty, Index)
- };
+ llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+ ConstantInt::get(Int32Ty, Index)};
llvm::Value *CpuValue = Builder.CreateGEP(STy, CpuModel, Idxs);
CpuValue = Builder.CreateAlignedLoad(CpuValue, CharUnits::fromQuantity(4));
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