[PATCH] D40023: [RISCV] Implement ABI lowering

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
Herald added subscribers: jordy.potman.lists, rbar, arichardson.

RISCVABIInfo is implemented in terms of XLen, supporting both RV32 and RV64. Unfortunately we need to count argument registers in the frontend in order to determine when to emit signext and zeroext attributes. Integer scalars are extended according to their type up to 32-bits and then sign-extended to XLen when passed in registers, but are anyext when passed on the stack. This patch only implements the base integer (soft float) ABIs.

For more information on the RISC-V ABI, see the ABI doc <https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md>, my golden model <https://github.com/lowRISC/riscv-calling-conv-model>, and the LLVM RISC-V calling convention patch <https://reviews.llvm.org/D39898#2d1595b4> (specifically the comment documenting frontend expectations).

It was necessary to modify CodeGenModule::ConstructAttributeList to ensure that signext is emitted for int32_t/uint32_t return values. Mips is the only other implementer of shouldSignExtUnsignedType but is unaffected, as unlike classifyArgumentType, classifyReturnType will not extend i32 values (@sdardis: is this a bug?).

@chandlerc, if you could help nominate appropriate reviewers I would appreciate it. I've CCed in those who are doing work on/with RISC-V LLVM and are well placed to review whether the RISC-V ABI and calling convention is implemented faithfully.


https://reviews.llvm.org/D40023

Files:
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/TargetInfo.cpp
  test/CodeGen/riscv32-abi.c
  test/CodeGen/riscv64-abi.c
  test/Driver/riscv32-toolchain.c
  test/Driver/riscv64-toolchain.c

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