[PATCH] D38672: [X86][AVX512] lowering shuffle f/i intrinsic - clang part

[Lama via Phabricator via cfe-commits]

lsaba added inline comments.


================
Comment at: lib/Headers/avx512fintrin.h:7207
+                                  3 + ((((imm) >> 2) & 0x3) * 4), \
+                                  8 + ((((imm) >> 4) & 0x3) * 4), \
+                                  9 + ((((imm) >> 4) & 0x3) * 4), \
----------------
This should start at 16 in order to get to B


================
Comment at: lib/Headers/avx512fintrin.h:7213
+                                  9 + ((((imm) >> 6) & 0x3) * 4), \
+                                  10 + ((((imm) >> 4) & 0x3) * 4), \
+                                  11 + ((((imm) >> 4) & 0x3) * 4)); })
----------------
this should be >>6?


================
Comment at: test/CodeGen/avx512f-builtins.c:4491
   // CHECK-LABEL: @test_mm512_shuffle_f32x4
-  // CHECK: @llvm.x86.avx512.mask.shuf.f32x4
+  // CHECK: shufflevector <16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
   return _mm512_shuffle_f32x4(__A, __B, 4); 
----------------
expected to be
shufflevector <16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 16, i32 17, i32 18, i32 19>
See comment on 
#define _mm512_shuffle_f32x4(A, B, imm) __extension__ ({ 


================
Comment at: test/CodeGen/avx512f-builtins.c:4496
 __m512 test_mm512_mask_shuffle_f32x4(__m512 __W, __mmask16 __U, __m512 __A, __m512 __B) {
   // CHECK-LABEL: @test_mm512_mask_shuffle_f32x4
+  // CHECK: shufflevector <16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
----------------
Same comment as above


https://reviews.llvm.org/D38672