[PATCH] D37568: [AMDGPU] Allow flexible register names in inline asm constraints

[Matt Arsenault via Phabricator via cfe-commits]

arsenm added inline comments.


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Comment at: test/Sema/inline-asm-validate-amdgpu.cl:38
+    __asm("v_add_f32_e32 v1, v2, v3" : "=v1"(ci) : "v2"(ai), "v3"(bi) : ); /// expected-error {{invalid output constraint '=v1' in asm}}
+    __asm("v_add_f32_e32 v1, v2, v3" : "=v1:2"(ci) : "v3:4"(ai), "v4:5"(bi) : );  // expected-error {{invalid output constraint '=v1:2' in asm}}
+
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arsenm wrote:
> I don't understand. The backend parsed syntax is v[3:4]. Why should v3:4 be valid? Also in this example you are using a 64-bit input to a 32-bit operand
i.e. this won't parse in the backend and is invalid. The brackets are required


https://reviews.llvm.org/D37568