[PATCH] D36371: [Clang][x86][Inline Asm] support for GCC style inline asm - Y<x> constraints

[coby via Phabricator via cfe-commits]

coby created this revision.

This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes https://reviews.llvm.org/D32505
llvm counterpart: https://reviews.llvm.org/D36369


Repository:
  rL LLVM

https://reviews.llvm.org/D36371

Files:
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/TargetInfo.cpp


Index: lib/CodeGen/TargetInfo.cpp
===================================================================
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -865,7 +866,10 @@
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                           StringRef Constraint,
                                           llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
+                     .Cases("y", "&y", "^Ym", true)
+                     .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
     if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
       // Invalid MMX constraint
       return nullptr;
Index: lib/Basic/Targets/X86.cpp
===================================================================
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -1346,7 +1346,9 @@
     switch (*Name) {
     default:
       return false;
+    case 'z':
     case '0': // First SSE register.
+    case '2':
     case 't': // Any SSE register, when SSE2 is enabled.
     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
     case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1435,12 +1437,19 @@
       return Size <= 64;
     case 'i':
     case 't':
-      // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
+    case '2':
+      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
+      // Any SSE register when SSE2 and up is available
       if (SSELevel >= AVX512F)
         return Size <= 512U;
       else if (SSELevel >= AVX)
         return Size <= 256U;
       return SSELevel >= SSE2 && Size <= 128U;
+    case 'z':
+    case '0':
+      // XMM0
+      if (SSELevel >= SSE1)
+        return Size <= 128U;
     }
   }
 
@@ -1475,6 +1484,12 @@
       // the return string.
       break;
     case 'k':
+    case 'm':
+    case 'i':
+    case 't':
+    case 'z':
+    case '0':
+    case '2':
       // "^" hints llvm that this is a 2 letter constraint.
       // "Constraint++" is used to promote the string iterator
       // to the next constraint.
Index: lib/Basic/Targets/X86.h
===================================================================
--- lib/Basic/Targets/X86.h
+++ lib/Basic/Targets/X86.h
@@ -435,9 +435,12 @@
     // In case the constraint is 'r' we need to return Expression
     case 'r':
       return Expression;
+    // Double letters Y<x> constraints
+    case 'Y':
+      if ((++I != E) && ((*I == '0') || (*I == 'z')))
+        return "xmm0";
     default:
-      // Default value if there is no constraint for the register
-      return "";
+      LLVM_FALLTHROUGH;
     }
     return "";
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36371.109910.patch
Type: text/x-patch
Size: 3024 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20170806/33621534/attachment.bin>