r299229 - [mips][msa] Range adjustment for ldi_b builtin function operand
Petar Jovanovic via cfe-commits
cfe-commits at lists.llvm.org
Fri Mar 31 09:16:44 PDT 2017
Author: petarj
Date: Fri Mar 31 11:16:43 2017
New Revision: 299229
URL: http://llvm.org/viewvc/llvm-project?rev=299229&view=rev
Log:
[mips][msa] Range adjustment for ldi_b builtin function operand
Reasoning behind this change was allowing the function to accept all values
from range [-128, 255] since all of them can be encoded in an 8bit wide
value.
This differs from the prior state where only range [-128, 127] was accepted,
where values were assumed to be signed, whereas now the actual
interpretation of the immediate is deferred to the consumer as required.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D31082
Modified:
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
cfe/trunk/test/CodeGen/builtins-mips-msa.c
Modified: cfe/trunk/lib/Sema/SemaChecking.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaChecking.cpp?rev=299229&r1=299228&r2=299229&view=diff
==============================================================================
--- cfe/trunk/lib/Sema/SemaChecking.cpp (original)
+++ cfe/trunk/lib/Sema/SemaChecking.cpp Fri Mar 31 11:16:43 2017
@@ -1640,7 +1640,7 @@ bool Sema::CheckMipsBuiltinFunctionCall(
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
// Memory offsets and immediate loads.
// These intrinsics take a signed 10 bit immediate.
- case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
+ case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 255; break;
case Mips::BI__builtin_msa_ldi_h:
case Mips::BI__builtin_msa_ldi_w:
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa-error.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips-msa-error.c?rev=299229&r1=299228&r2=299229&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/builtins-mips-msa-error.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips-msa-error.c Fri Mar 31 11:16:43 2017
@@ -119,7 +119,7 @@ void test(void) {
v4i32_r = __msa_ld_w(&v4i32_a, 512); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, 512); // expected-error {{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(512); // expected-error {{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(256); // expected-error {{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(512); // expected-error {{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(512); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(512); // expected-error {{argument should be a value from -512 to 511}}
@@ -310,7 +310,7 @@ void test(void) {
v4i32_r = __msa_ld_w(&v4i32_a, -513); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ld_d(&v2i64_a, -513); // expected-error {{argument should be a value from -512 to 511}}
- v16i8_r = __msa_ldi_b(-513); // expected-error {{argument should be a value from -512 to 511}}
+ v16i8_r = __msa_ldi_b(-129); // expected-error {{argument should be a value from -128 to 255}}
v8i16_r = __msa_ldi_h(-513); // expected-error {{argument should be a value from -512 to 511}}
v4i32_r = __msa_ldi_w(-513); // expected-error {{argument should be a value from -512 to 511}}
v2i64_r = __msa_ldi_d(-513); // expected-error {{argument should be a value from -512 to 511}}
Modified: cfe/trunk/test/CodeGen/builtins-mips-msa.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-mips-msa.c?rev=299229&r1=299228&r2=299229&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/builtins-mips-msa.c (original)
+++ cfe/trunk/test/CodeGen/builtins-mips-msa.c Fri Mar 31 11:16:43 2017
@@ -526,6 +526,8 @@ void test(void) {
v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2 x i64> @llvm.mips.ld.d(
v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(-128); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
+ v16i8_r = __msa_ldi_b(255); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
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