r298956 - Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors:

[Eric Christopher via cfe-commits]

Hi Craig, Quentin, Jim,

Just bringing this patch to your attention here. I haven't turned it off in
the backend since some processors do support it and we want to allow the
code generation, with this change we simply make the user use -mrtm to get
the functionality for now.

Question: Do we want to split the haswell and broadwell cpu to handle this
different feature set or just leave it as an optional "enable it yourself"
since it's an errata fix?

I went ahead and committed with this question outstanding so that users
won't get illegal instructions if they happen to have the affected units.

-eric

On Tue, Mar 28, 2017 at 4:15 PM Eric Christopher via cfe-commits <
cfe-commits at lists.llvm.org> wrote:

> Author: echristo
> Date: Tue Mar 28 18:03:19 2017
> New Revision: 298956
>
> URL: http://llvm.org/viewvc/llvm-project?rev=298956&view=rev
> Log:
> Default enable the rtm feature only on skylake and later for now because
> Intel disabled the feature on some haswell and broadwell processors:
>
>
> http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf
>
> the -mrtm option will still work normally.
>
> Modified:
>     cfe/trunk/lib/Basic/Targets.cpp
>     cfe/trunk/test/Preprocessor/predefined-arch-macros.c
>
> Modified: cfe/trunk/lib/Basic/Targets.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=298956&r1=298955&r2=298956&view=diff
>
> ==============================================================================
> --- cfe/trunk/lib/Basic/Targets.cpp (original)
> +++ cfe/trunk/lib/Basic/Targets.cpp Tue Mar 28 18:03:19 2017
> @@ -3194,6 +3194,7 @@ bool X86TargetInfo::initFeatureMap(
>      setFeatureEnabledImpl(Features, "mpx", true);
>      setFeatureEnabledImpl(Features, "sgx", true);
>      setFeatureEnabledImpl(Features, "clflushopt", true);
> +    setFeatureEnabledImpl(Features, "rtm", true);
>      LLVM_FALLTHROUGH;
>    case CK_Broadwell:
>      setFeatureEnabledImpl(Features, "rdseed", true);
> @@ -3204,7 +3205,6 @@ bool X86TargetInfo::initFeatureMap(
>      setFeatureEnabledImpl(Features, "lzcnt", true);
>      setFeatureEnabledImpl(Features, "bmi", true);
>      setFeatureEnabledImpl(Features, "bmi2", true);
> -    setFeatureEnabledImpl(Features, "rtm", true);
>      setFeatureEnabledImpl(Features, "fma", true);
>      setFeatureEnabledImpl(Features, "movbe", true);
>      LLVM_FALLTHROUGH;
>
> Modified: cfe/trunk/test/Preprocessor/predefined-arch-macros.c
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/predefined-arch-macros.c?rev=298956&r1=298955&r2=298956&view=diff
>
> ==============================================================================
> --- cfe/trunk/test/Preprocessor/predefined-arch-macros.c (original)
> +++ cfe/trunk/test/Preprocessor/predefined-arch-macros.c Tue Mar 28
> 18:03:19 2017
> @@ -525,7 +525,6 @@
>  // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1
>  // CHECK_CORE_AVX2_M32: #define __POPCNT__ 1
>  // CHECK_CORE_AVX2_M32: #define __RDRND__ 1
> -// CHECK_CORE_AVX2_M32: #define __RTM__ 1
>  // CHECK_CORE_AVX2_M32: #define __SSE2__ 1
>  // CHECK_CORE_AVX2_M32: #define __SSE3__ 1
>  // CHECK_CORE_AVX2_M32: #define __SSE4_1__ 1
> @@ -555,7 +554,6 @@
>  // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1
>  // CHECK_CORE_AVX2_M64: #define __POPCNT__ 1
>  // CHECK_CORE_AVX2_M64: #define __RDRND__ 1
> -// CHECK_CORE_AVX2_M64: #define __RTM__ 1
>  // CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1
>  // CHECK_CORE_AVX2_M64: #define __SSE2__ 1
>  // CHECK_CORE_AVX2_M64: #define __SSE3__ 1
> @@ -591,7 +589,6 @@
>  // CHECK_BROADWELL_M32: #define __POPCNT__ 1
>  // CHECK_BROADWELL_M32: #define __RDRND__ 1
>  // CHECK_BROADWELL_M32: #define __RDSEED__ 1
> -// CHECK_BROADWELL_M32: #define __RTM__ 1
>  // CHECK_BROADWELL_M32: #define __SSE2__ 1
>  // CHECK_BROADWELL_M32: #define __SSE3__ 1
>  // CHECK_BROADWELL_M32: #define __SSE4_1__ 1
> @@ -623,7 +620,6 @@
>  // CHECK_BROADWELL_M64: #define __POPCNT__ 1
>  // CHECK_BROADWELL_M64: #define __RDRND__ 1
>  // CHECK_BROADWELL_M64: #define __RDSEED__ 1
> -// CHECK_BROADWELL_M64: #define __RTM__ 1
>  // CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1
>  // CHECK_BROADWELL_M64: #define __SSE2__ 1
>  // CHECK_BROADWELL_M64: #define __SSE3__ 1
>
>
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