r298767 - [AMDGPU] Switch address space mapping by triple environment amdgiz

Eric Christopher via cfe-commits cfe-commits at lists.llvm.org
Fri Mar 24 22:52:04 PDT 2017


On Fri, Mar 24, 2017 at 8:58 PM Yaxun Liu via cfe-commits <
cfe-commits at lists.llvm.org> wrote:

> Author: yaxunl
> Date: Fri Mar 24 22:46:25 2017
> New Revision: 298767
>
> URL: http://llvm.org/viewvc/llvm-project?rev=298767&view=rev
> Log:
> [AMDGPU] Switch address space mapping by triple environment amdgiz
>
> For target environment amdgiz and amdgizcl (giz means Generic Is Zero),
> AMDGPU will use new address space mapping where generic address space is 0
> and private address space is 5. The data layout is also changed
> correspondingly.
>
> Differential Revision: https://reviews.llvm.org/D31210
>
> Added:
>     cfe/trunk/test/CodeGenOpenCL/amdgpu-env-amdgiz.cl
> Modified:
>     cfe/trunk/lib/Basic/Targets.cpp
>
> Modified: cfe/trunk/lib/Basic/Targets.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=298767&r1=298766&r2=298767&view=diff
>
> ==============================================================================
> --- cfe/trunk/lib/Basic/Targets.cpp (original)
> +++ cfe/trunk/lib/Basic/Targets.cpp Fri Mar 24 22:46:25 2017
> @@ -2027,14 +2027,23 @@ ArrayRef<const char *> NVPTXTargetInfo::
>    return llvm::makeArrayRef(GCCRegNames);
>  }
>
> -static const unsigned AMDGPUAddrSpaceMap[] = {
> -  1,    // opencl_global
> -  3,    // opencl_local
> -  2,    // opencl_constant
> -  4,    // opencl_generic
> -  1,    // cuda_device
> -  2,    // cuda_constant
> -  3     // cuda_shared
> +static const LangAS::Map AMDGPUPrivateIsZeroMap = {
> +    1,  // opencl_global
> +    3,  // opencl_local
> +    2,  // opencl_constant
> +    4,  // opencl_generic
> +    1,  // cuda_device
> +    2,  // cuda_constant
> +    3   // cuda_shared
> +};
> +static const LangAS::Map AMDGPUGenericIsZeroMap = {
> +    1,  // opencl_global
> +    3,  // opencl_local
> +    4,  // opencl_constant
> +    0,  // opencl_generic
> +    1,  // cuda_device
> +    4,  // cuda_constant
> +    3   // cuda_shared
>  };
>
>  // If you edit the description strings, make sure you update
> @@ -2044,15 +2053,39 @@ static const char *const DataLayoutStrin
>    "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
>    "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
>
> -static const char *const DataLayoutStringSI =
> +static const char *const DataLayoutStringSIPrivateIsZero =
>    "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
>    "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
>    "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
>
> +static const char *const DataLayoutStringSIGenericIsZero =
> +  "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
> +  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
> +  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
> +
>  class AMDGPUTargetInfo final : public TargetInfo {
>    static const Builtin::Info BuiltinInfo[];
>    static const char * const GCCRegNames[];
>
> +  struct AddrSpace {
> +    unsigned Generic, Global, Local, Constant, Private;
> +    AddrSpace(bool IsGenericZero_ = false){
> +      if (IsGenericZero_) {
> +        Generic   = 0;
> +        Global    = 1;
> +        Local     = 3;
> +        Constant  = 4;
> +        Private   = 5;
> +      } else {
> +        Generic   = 4;
> +        Global    = 1;
> +        Local     = 3;
> +        Constant  = 2;
> +        Private   = 0;
> +      }
> +    }
> +  };
> +
>    /// \brief The GPU profiles supported by the AMDGPU target.
>    enum GPUKind {
>      GK_NONE,
> @@ -2079,6 +2112,10 @@ class AMDGPUTargetInfo final : public Ta
>      return TT.getArch() == llvm::Triple::amdgcn;
>    }
>
> +  static bool isGenericZero(const llvm::Triple &TT) {
> +    return TT.getEnvironmentName() == "amdgiz" ||
> +        TT.getEnvironmentName() == "amdgizcl";
> +  }
>  public:
>    AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
>      : TargetInfo(Triple) ,
> @@ -2086,17 +2123,21 @@ public:
>        hasFP64(false),
>        hasFMAF(false),
>        hasLDEXPF(false),
> -      hasFullSpeedFP32Denorms(false){
> +      hasFullSpeedFP32Denorms(false),
> +      AS(isGenericZero(Triple)){
>      if (getTriple().getArch() == llvm::Triple::amdgcn) {
>        hasFP64 = true;
>        hasFMAF = true;
>        hasLDEXPF = true;
>      }
> -
> +    auto IsGenericZero = isGenericZero(Triple);
>      resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
> -                    DataLayoutStringSI : DataLayoutStringR600);
> +                    (IsGenericZero ? DataLayoutStringSIGenericIsZero :
> +                        DataLayoutStringSIPrivateIsZero)
> +                    : DataLayoutStringR600);
>
> -    AddrSpaceMap = &AMDGPUAddrSpaceMap;
> +    AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap :
> +        &AMDGPUPrivateIsZeroMap;
>      UseAddrSpaceMapMangling = true;
>    }
>
> @@ -2104,14 +2145,10 @@ public:
>      if (GPU <= GK_CAYMAN)
>        return 32;
>
> -    switch(AddrSpace) {
> -      default:
> -        return 64;
> -      case 0:
> -      case 3:
> -      case 5:
> -        return 32;
> +    if (AddrSpace == AS.Private || AddrSpace == AS.Local) {
> +      return 32;
>      }
> +    return 64;
>    }
>
>    uint64_t getMaxPointerWidth() const override {
> @@ -2304,12 +2341,13 @@ public:
>    /// DWARF.
>    Optional<unsigned> getDWARFAddressSpace(
>        unsigned AddressSpace) const override {
> -    switch (AddressSpace) {
> -    case 0: // LLVM Private.
> -      return 1; // DWARF Private.
> -    case 3: // LLVM Local.
> -      return 2; // DWARF Local.
> -    default:
> +    const unsigned DWARF_Private = 1;
> +    const unsigned DWARF_Local   = 2;
> +    if (AddressSpace == AS.Private) {
> +      return DWARF_Private;
> +    } else if (AddressSpace == AS.Local) {
> +      return DWARF_Local;
> +    } else {
>        return None;
>      }
>    }
> @@ -2330,6 +2368,8 @@ public:
>    uint64_t getNullPointerValue(unsigned AS) const override {
>      return AS == LangAS::opencl_local ? ~0 : 0;
>    }
> +
> +  const AddrSpace AS;
>

Is there some reason to have this:

a) At the end of the class,

and

b) public?

Thanks!

-eric


>  };
>
>  const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
>
> Added: cfe/trunk/test/CodeGenOpenCL/amdgpu-env-amdgiz.cl
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/amdgpu-env-amdgiz.cl?rev=298767&view=auto
>
> ==============================================================================
> --- cfe/trunk/test/CodeGenOpenCL/amdgpu-env-amdgiz.cl (added)
> +++ cfe/trunk/test/CodeGenOpenCL/amdgpu-env-amdgiz.cl Fri Mar 24 22:46:25
> 2017
> @@ -0,0 +1,9 @@
> +// RUN: %clang_cc1 %s -O0 -triple amdgcn -emit-llvm -o - | FileCheck %s
> +// RUN: %clang_cc1 %s -O0 -triple amdgcn---opencl -emit-llvm -o - |
> FileCheck %s
> +// RUN: %clang_cc1 %s -O0 -triple amdgcn---amdgiz -emit-llvm -o - |
> FileCheck -check-prefix=GIZ %s
> +// RUN: %clang_cc1 %s -O0 -triple amdgcn---amdgizcl -emit-llvm -o - |
> FileCheck -check-prefix=GIZ %s
> +
> +// CHECK: target datalayout =
> "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
> +// GIZ: target datalayout =
> "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
> +void foo(void) {}
> +
>
>
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