r294176 - [AVR] Add support for the full set of inline asm constraints
Dylan McKay via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 6 01:01:59 PST 2017
Author: dylanmckay
Date: Mon Feb 6 03:01:59 2017
New Revision: 294176
URL: http://llvm.org/viewvc/llvm-project?rev=294176&view=rev
Log:
[AVR] Add support for the full set of inline asm constraints
Summary:
Previously the method would simply return false, causing every single
inline assembly constraint to trigger a compile error.
This adds inline assembly constraint support for the AVR target.
This patch is derived from the code in
AVRISelLowering::getConstraintType.
More details can be found on the AVR-GCC reference wiki
http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
Reviewers: jroelofs, asl
Reviewed By: asl
Subscribers: asl, ahatanak, saaadhu, cfe-commits
Differential Revision: https://reviews.llvm.org/D28344
Added:
cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=294176&r1=294175&r2=294176&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Mon Feb 6 03:01:59 2017
@@ -8517,6 +8517,57 @@ public:
bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const override {
+ // There aren't any multi-character AVR specific constraints.
+ if (StringRef(Name).size() > 1) return false;
+
+ switch (*Name) {
+ default: return false;
+ case 'a': // Simple upper registers
+ case 'b': // Base pointer registers pairs
+ case 'd': // Upper register
+ case 'l': // Lower registers
+ case 'e': // Pointer register pairs
+ case 'q': // Stack pointer register
+ case 'r': // Any register
+ case 'w': // Special upper register pairs
+ case 't': // Temporary register
+ case 'x': case 'X': // Pointer register pair X
+ case 'y': case 'Y': // Pointer register pair Y
+ case 'z': case 'Z': // Pointer register pair Z
+ Info.setAllowsRegister();
+ return true;
+ case 'I': // 6-bit positive integer constant
+ Info.setRequiresImmediate(0, 63);
+ return true;
+ case 'J': // 6-bit negative integer constant
+ Info.setRequiresImmediate(-63, 0);
+ return true;
+ case 'K': // Integer constant (Range: 2)
+ Info.setRequiresImmediate(2);
+ return true;
+ case 'L': // Integer constant (Range: 0)
+ Info.setRequiresImmediate(0);
+ return true;
+ case 'M': // 8-bit integer constant
+ Info.setRequiresImmediate(0, 0xff);
+ return true;
+ case 'N': // Integer constant (Range: -1)
+ Info.setRequiresImmediate(-1);
+ return true;
+ case 'O': // Integer constant (Range: 8, 16, 24)
+ Info.setRequiresImmediate({8, 16, 24});
+ return true;
+ case 'P': // Integer constant (Range: 1)
+ Info.setRequiresImmediate(1);
+ return true;
+ case 'R': // Integer constant (Range: -6 to 5)
+ Info.setRequiresImmediate(-6, 5);
+ return true;
+ case 'G': // Floating point constant
+ case 'Q': // A memory address based on Y or Z pointer with displacement.
+ return true;
+ }
+
return false;
}
Added: cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c?rev=294176&view=auto
==============================================================================
--- cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c (added)
+++ cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c Mon Feb 6 03:01:59 2017
@@ -0,0 +1,124 @@
+// REQUIRES: avr-registered-target
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void a() {
+ // CHECK: call void asm sideeffect "add r5, $0", "a"(i16 %0)
+ asm("add r5, %0" :: "a"(data));
+}
+
+void b() {
+ // CHECK: call void asm sideeffect "add r5, $0", "b"(i16 %0)
+ asm("add r5, %0" :: "b"(data));
+}
+
+void d() {
+ // CHECK: call void asm sideeffect "add r5, $0", "d"(i16 %0)
+ asm("add r5, %0" :: "d"(data));
+}
+
+void l() {
+ // CHECK: call void asm sideeffect "add r5, $0", "l"(i16 %0)
+ asm("add r5, %0" :: "l"(data));
+}
+
+void e() {
+ // CHECK: call void asm sideeffect "add r5, $0", "e"(i16 %0)
+ asm("add r5, %0" :: "e"(data));
+}
+
+void q() {
+ // CHECK: call void asm sideeffect "add r5, $0", "q"(i16 %0)
+ asm("add r5, %0" :: "q"(data));
+}
+
+void r() {
+ // CHECK: call void asm sideeffect "add r5, $0", "r"(i16 %0)
+ asm("add r5, %0" :: "r"(data));
+}
+
+void w() {
+ // CHECK: call void asm sideeffect "add r5, $0", "w"(i16 %0)
+ asm("add r5, %0" :: "w"(data));
+}
+
+void t() {
+ // CHECK: call void asm sideeffect "add r5, $0", "t"(i16 %0)
+ asm("add r5, %0" :: "t"(data));
+}
+
+void x() {
+ // CHECK: call void asm sideeffect "add r5, $0", "x"(i16 %0)
+ asm("add r5, %0" :: "x"(data));
+}
+
+void y() {
+ // CHECK: call void asm sideeffect "add r5, $0", "y"(i16 %0)
+ asm("add r5, %0" :: "y"(data));
+}
+
+void z() {
+ // CHECK: call void asm sideeffect "add r5, $0", "z"(i16 %0)
+ asm("add r5, %0" :: "z"(data));
+}
+
+void I() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "I"(i16 50)
+ asm("subi r30, %0" :: "I"(50));
+}
+
+void J() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "J"(i16 -50)
+ asm("subi r30, %0" :: "J"(-50));
+}
+
+void K() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "K"(i16 2)
+ asm("subi r30, %0" :: "K"(2));
+}
+
+void L() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "L"(i16 0)
+ asm("subi r30, %0" :: "L"(0));
+}
+
+void M() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "M"(i16 255)
+ asm("subi r30, %0" :: "M"(255));
+}
+
+void O() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "O"(i16 16)
+ asm("subi r30, %0" :: "O"(16));
+}
+
+void P() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "P"(i16 1)
+ asm("subi r30, %0" :: "P"(1));
+}
+
+void R() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "R"(i16 -3)
+ asm("subi r30, %0" :: "R"(-3));
+}
+
+void G() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "G"(i16 50)
+ asm("subi r30, %0" :: "G"(50));
+}
+
+void Q() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "Q"(i16 50)
+ asm("subi r30, %0" :: "Q"(50));
+}
+
+void ra() {
+ // CHECK: call void asm sideeffect "subi r30, $0", "ra"(i16 50)
+ asm("subi r30, %0" :: "ra"(50));
+}
+
+void ora() {
+ // CHECK: call i16 asm "subi r30, $0", "=ra"()
+ asm("subi r30, %0" : "=ra"(data));
+}
Added: cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c?rev=294176&view=auto
==============================================================================
--- cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c (added)
+++ cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c Mon Feb 6 03:01:59 2017
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -verify %s
+
+const unsigned char val = 0;
+
+int foo() {
+ __asm__ volatile("foo %0, 1" : : "fo" (val)); // expected-error {{invalid input constraint 'fo' in asm}}
+ __asm__ volatile("foo %0, 1" : : "Nd" (val)); // expected-error {{invalid input constraint 'Nd' in asm}}
+}
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