[PATCH] D27529: Correct Vectorcall Register passing and HVA Behavior

[David Majnemer via Phabricator via cfe-commits]

majnemer added inline comments.


================
Comment at: lib/CodeGen/TargetInfo.cpp:1688
+    for (auto &I : FI.arguments()) {
+      if(Count < 6)
+        I.info = reclassifyHvaArgType(I.type, State, I.info);
----------------
Formatting.


================
Comment at: lib/CodeGen/TargetInfo.cpp:3799-3804
+      } else if (IsReturnType)
+        return ABIArgInfo::getExpand();
+      else if (!Ty->isBuiltinType() && !Ty->isVectorType())
+        // HVAs are delayed and reclassified in the 2nd step.
+        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
     }
----------------
Please consistently brace here.


================
Comment at: lib/CodeGen/TargetInfo.cpp:3871
+    for (auto &I : FI.arguments()) {
+      if (Count < 6)
+        I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
----------------
majnemer wrote:
> And here,
I was OK with `6` showing up in prior code because there was a comment but there isn't such a comment down here.  Maybe we should have this `6` live in an enum?


================
Comment at: lib/CodeGen/TargetInfo.cpp:3871-3879
+      if (Count < 6)
+        I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
+      else {
+        // Since these cannot be passed in registers, pretend no registers
+        // are left.
+        unsigned ZeroSSERegsAvail= 0;
+        I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
----------------
And here,


https://reviews.llvm.org/D27529