[PATCH] D26534: [PPC] add altivec.h functions for converting a vector of half precision to a vector of single precision

[Sean Fertile via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL286863: [PPC] altivec.h functions for converting half precision to single precision. (authored by sfertile).

Changed prior to commit:
  https://reviews.llvm.org/D26534?vs=77581&id=77842#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D26534

Files:
  cfe/trunk/include/clang/Basic/BuiltinsPPC.def
  cfe/trunk/lib/Headers/altivec.h
  cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c


Index: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
===================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def
@@ -402,6 +402,7 @@
 BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "")
 
 BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "")
+BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "")
 
 // Vector Test Data Class builtins
 BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "")
Index: cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
===================================================================
--- cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
+++ cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
@@ -967,3 +967,21 @@
 // CHECK-NEXT: ret <2 x i64>
   return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL);
 }
+vector float test88(void) {
+// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3>
+// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef>
+// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
+// CHECK-LE-NEXT: ret <4 x float>
+  return vec_extract_fp32_from_shorth(vusa);
+}
+vector float test89(void) {
+// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7>
+// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
+// CHECK-BE-NEXT: ret <4 x float>
+// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
+// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})
+// CHECK-LE-NEXT: ret <4 x float>
+  return vec_extract_fp32_from_shortl(vusa);
+}
Index: cfe/trunk/lib/Headers/altivec.h
===================================================================
--- cfe/trunk/lib/Headers/altivec.h
+++ cfe/trunk/lib/Headers/altivec.h
@@ -12322,6 +12322,27 @@
   return __builtin_vsx_xvxsigdp(__a);
 }
 
+static __inline__ vector float __ATTRS_o_ai
+vec_extract_fp32_from_shorth(vector unsigned short __a) {
+  vector unsigned short __b =
+#ifdef __LITTLE_ENDIAN__
+            __builtin_shufflevector(__a, __a, 0, -1, 1, -1, 2, -1, 3, -1);
+#else
+            __builtin_shufflevector(__a, __a, -1, 0, -1, 1, -1, 2, -1, 3);
+#endif
+  return __builtin_vsx_xvcvhpsp(__b);
+}
+
+static __inline__ vector float __ATTRS_o_ai
+vec_extract_fp32_from_shortl(vector unsigned short __a) {
+  vector unsigned short __b =
+#ifdef __LITTLE_ENDIAN__
+            __builtin_shufflevector(__a, __a, 4, -1, 5, -1, 6, -1, 7, -1);
+#else
+            __builtin_shufflevector(__a, __a, -1, 4, -1, 5, -1, 6, -1, 7);
+#endif
+  return __builtin_vsx_xvcvhpsp(__b);
+}
 #endif /* __POWER9_VECTOR__ */
 
 /* vec_insert */


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