[PATCH] D21021: [Clang][AVX512][BuiltIn]Adding intrinsics move_{sd|ss} to clang
Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Oct 5 06:05:15 PDT 2016
This revision was automatically updated to reflect the committed changes.
Closed by commit rL283314: [Clang][AVX512][BuiltIn]Adding missing intrinsics move_{sd|ss} to clang (authored by mzuckerm).
Changed prior to commit:
https://reviews.llvm.org/D21021?vs=59720&id=73638#toc
Repository:
rL LLVM
https://reviews.llvm.org/D21021
Files:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/test/CodeGen/avx512f-builtins.c
Index: cfe/trunk/include/clang/Basic/BuiltinsX86.def
===================================================================
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def
@@ -2021,6 +2021,8 @@
TARGET_BUILTIN(__builtin_ia32_expandsf512_mask, "V16fV16fV16fUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_expandsi512_mask, "V16iV16iV16iUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_cvtps2pd512_mask, "V8dV8fV8dUcIi","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_movss_mask, "V4fV4fV4fV4fUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_movsd_mask, "V2dV2dV2dV2dUc","","avx512f")
TARGET_BUILTIN(__builtin_ia32_compressstoredf512_mask, "vV8d*V8dUc","","avx512f")
TARGET_BUILTIN(__builtin_ia32_compressstoredi512_mask, "vV8LLi*V8LLiUc","","avx512f")
TARGET_BUILTIN(__builtin_ia32_compressstoresf512_mask, "vV16f*V16fUs","","avx512f")
Index: cfe/trunk/test/CodeGen/avx512f-builtins.c
===================================================================
--- cfe/trunk/test/CodeGen/avx512f-builtins.c
+++ cfe/trunk/test/CodeGen/avx512f-builtins.c
@@ -7863,6 +7863,34 @@
return _mm512_setzero_pd();
}
+__m128 test_mm_mask_move_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
+{
+ // CHECK-LABEL: @test_mm_mask_move_ss
+ // CHECK: @llvm.x86.avx512.mask.move.ss
+ return _mm_mask_move_ss ( __W, __U, __A, __B);
+}
+
+__m128 test_mm_maskz_move_ss (__mmask8 __U, __m128 __A, __m128 __B)
+{
+ // CHECK-LABEL: @test_mm_maskz_move_ss
+ // CHECK: @llvm.x86.avx512.mask.move.ss
+ return _mm_maskz_move_ss (__U, __A, __B);
+}
+
+__m128d test_mm_mask_move_sd (__m128 __W, __mmask8 __U, __m128d __A, __m128d __B)
+{
+ // CHECK-LABEL: @test_mm_mask_move_sd
+ // CHECK: @llvm.x86.avx512.mask.move.sd
+ return _mm_mask_move_sd ( __W, __U, __A, __B);
+}
+
+__m128d test_mm_maskz_move_sd (__mmask8 __U, __m128d __A, __m128d __B)
+{
+ // CHECK-LABEL: @test_mm_maskz_move_sd
+ // CHECK: @llvm.x86.avx512.mask.move.sd
+ return _mm_maskz_move_sd (__U, __A, __B);
+}
+
__m512d test_mm512_abs_pd(__m512d a){
// CHECK-LABEL: @test_mm512_abs_pd
// CHECK: and <8 x i64>
Index: cfe/trunk/lib/Headers/avx512fintrin.h
===================================================================
--- cfe/trunk/lib/Headers/avx512fintrin.h
+++ cfe/trunk/lib/Headers/avx512fintrin.h
@@ -9140,6 +9140,40 @@
(__v16sf)_mm512_setzero_ps());
}
+static __inline__ __m128 __DEFAULT_FN_ATTRS
+_mm_mask_move_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
+{
+ return (__m128) __builtin_ia32_movss_mask ((__v4sf) __A, (__v4sf) __B,
+ (__v4sf) __W,
+ (__mmask8) __U);
+}
+
+static __inline__ __m128 __DEFAULT_FN_ATTRS
+_mm_maskz_move_ss (__mmask8 __U, __m128 __A, __m128 __B)
+{
+ return (__m128) __builtin_ia32_movss_mask ((__v4sf) __A, (__v4sf) __B,
+ (__v4sf)
+ _mm_setzero_si128(),
+ (__mmask8) __U);
+}
+
+static __inline__ __m128d __DEFAULT_FN_ATTRS
+_mm_mask_move_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
+{
+ return (__m128d) __builtin_ia32_movsd_mask ((__v2df) __A, (__v2df) __B,
+ (__v2df) __W,
+ (__mmask8) __U);
+}
+
+static __inline__ __m128d __DEFAULT_FN_ATTRS
+_mm_maskz_move_sd (__mmask8 __U, __m128d __A, __m128d __B)
+{
+ return (__m128d) __builtin_ia32_movsd_mask ((__v2df) __A, (__v2df) __B,
+ (__v2df)
+ _mm_setzero_pd (),
+ (__mmask8) __U);
+}
+
#define _mm512_shuffle_epi32(A, I) __extension__ ({ \
(__m512i)__builtin_shufflevector((__v16si)(__m512i)(A), \
(__v16si)_mm512_undefined_epi32(), \
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