[PATCH] D17933: Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

[Richard Smith via cfe-commits]

rsmith added a subscriber: rsmith.

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Comment at: lib/Basic/Targets.cpp:4080
@@ -4079,1 +4079,3 @@
+    // x86-64 has atomics up to 16 bytes, when the HasCX16 target
+    // feature is enabled, 64 otherwise.
     MaxAtomicPromoteWidth = 128;
----------------
... where by 64, you mean 8, right? :)

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Comment at: test/CodeGen/atomic-ops.c:1
@@ -1,2 +1,2 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 | FileCheck %s
 // REQUIRES: x86-registered-target
----------------
Why do you need a -target-cpu i686 in addition to the i686 triple?

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Comment at: test/Preprocessor/arm-target-features.c:108-118
@@ -107,2 +107,13 @@
 // V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
-// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+// V8M_BASELINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_BASELINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_BASELINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// V8M_BASELINE: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
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Maybe drop the #define on these lines for consistency with the surrounding tests?

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Comment at: test/Preprocessor/init.c:3295
@@ -3292,1 +3294,3 @@
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
 // MIPSN32BE: #define __GNUC_MINOR__ 2
----------------
Can you add a `MIPSN32BE-NOT: ` for the 16 byte form? Likewise for the below cases.


http://reviews.llvm.org/D17933