[PATCH] D15223: [ARM] [AARCH64] Add CodeGen IR tests for {VS}QRDML{AS}H v8.1a intrinsics.

[James Molloy via cfe-commits]

Fwiw, I am certainly in Tim'a camp here! Writing a test for that output is
doable, and if that's what people want then that's what we'll do. But it's
certainly not nice or readable !
On Mon, 14 Dec 2015 at 19:25, Tim Northover via cfe-commits <
cfe-commits at lists.llvm.org> wrote:

> On 14 December 2015 at 11:12, Eric Christopher <echristo at gmail.com> wrote:
> > There really is a pretty good separation of concerns and for a lot if not
> > most of the tests here all the difference is checking is the arguments,
> > keeping track of an alloca and making sure that goes is pretty simple and
> > not really hard for a test.
>
> And the rest! This us the output for a trivial function: vqrdmulh_s16:
>
> define <4 x i16> @foo(<4 x i16> %l, <4 x i16> %r) #0 {
> entry:
>   %__p0.addr.i = alloca <4 x i16>, align 8
>   %__p1.addr.i = alloca <4 x i16>, align 8
>   %__ret.i = alloca <4 x i16>, align 8
>   %l.addr = alloca <4 x i16>, align 8
>   %r.addr = alloca <4 x i16>, align 8
>   store <4 x i16> %l, <4 x i16>* %l.addr, align 8
>   store <4 x i16> %r, <4 x i16>* %r.addr, align 8
>   %0 = load <4 x i16>, <4 x i16>* %l.addr, align 8
>   %1 = load <4 x i16>, <4 x i16>* %r.addr, align 8
>   store <4 x i16> %0, <4 x i16>* %__p0.addr.i, align 8
>   store <4 x i16> %1, <4 x i16>* %__p1.addr.i, align 8
>   %2 = load <4 x i16>, <4 x i16>* %__p0.addr.i, align 8
>   %3 = bitcast <4 x i16> %2 to <8 x i8>
>   %4 = load <4 x i16>, <4 x i16>* %__p1.addr.i, align 8
>   %5 = bitcast <4 x i16> %4 to <8 x i8>
>   %vqrdmulh_v.i = bitcast <8 x i8> %3 to <4 x i16>
>   %vqrdmulh_v1.i = bitcast <8 x i8> %5 to <4 x i16>
>   %vqrdmulh_v2.i = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x
> i16> %vqrdmulh_v.i, <4 x i16> %vqrdmulh_v1.i) #2
>   %vqrdmulh_v3.i = bitcast <4 x i16> %vqrdmulh_v2.i to <8 x i8>
>   %6 = bitcast <8 x i8> %vqrdmulh_v3.i to <4 x i16>
>   store <4 x i16> %6, <4 x i16>* %__ret.i, align 8
>   %7 = load <4 x i16>, <4 x i16>* %__ret.i, align 8
>   ret <4 x i16> %7
> }
>
> Is that right? Hope so, but I'm buggered if I know. And when anyone
> looks at a test based on that they've got to thread 3 datapaths
> through about 6 stages each without getting confused to work it out.
> Possible, but for the tiny beneficial fuzzies we get from not running
> opt, not worth it in my opinion.
>
> Tim.
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