r241666 - [CodeGen] Don't crash classifying a union of an AVX vector and an int

David Majnemer david.majnemer at gmail.com
Tue Jul 7 22:07:05 PDT 2015


Author: majnemer
Date: Wed Jul  8 00:07:05 2015
New Revision: 241666

URL: http://llvm.org/viewvc/llvm-project?rev=241666&view=rev
Log:
[CodeGen] Don't crash classifying a union of an AVX vector and an int

We forgot to run postMerge after decided that the union had to be
classified as MEMORY.  This left us with Lo == MEMORY and Hi == SSEUp
which is an invalid combination.

This fixes PR24021.

Differential Revision: http://reviews.llvm.org/D10908

Modified:
    cfe/trunk/lib/CodeGen/TargetInfo.cpp
    cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=241666&r1=241665&r2=241666&view=diff
==============================================================================
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Wed Jul  8 00:07:05 2015
@@ -2094,11 +2094,13 @@ void X86_64ABIInfo::classify(QualType Ty
       //
       if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
         Lo = Memory;
+        postMerge(Size, Lo, Hi);
         return;
       }
       // Note, skip this test for bit-fields, see below.
       if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
         Lo = Memory;
+        postMerge(Size, Lo, Hi);
         return;
       }
 

Modified: cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp?rev=241666&r1=241665&r2=241666&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp Wed Jul  8 00:07:05 2015
@@ -50,3 +50,12 @@ UU2 PR23082(UU2 x) {
   return x;
 }
 }
+
+namespace test3 {
+union U {
+  __attribute__((__vector_size__(32))) float f1;
+  int f2;
+};
+// CHECK: define i32 @_ZN5test31fENS_1UE({{.*}}* byval align 32
+int f(U u) { return u.f2; }
+}





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