[PATCH] [PPC64] Add 64-bit Vector Integer Arithmetic Instructions

[Nemanja Ivanovic]

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Comment at: include/clang/Basic/BuiltinsPPC.def:220
@@ -204,1 +219,3 @@
 BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "")
+BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "")
+BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "")
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Similar comment about the return type.

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Comment at: lib/Headers/altivec.h:2913
@@ +2912,3 @@
+static vector long long __ATTRS_o_ai
+vec_vmaxsd(vector bool long long __a, vector long long __b)
+{
----------------
The ABI does not list any overloads for vmaxsd and vmaxud builtins other than the ones that take two vector [un]signed long long. Furthermore, gcc provides only the single overload as listed in the ABI. Are these for compatibility with something else?

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Comment at: lib/Headers/altivec.h:3462
@@ +3461,3 @@
+
+static vector long long __ATTRS_o_ai
+vec_min(vector bool long long __a, vector long long __b)
----------------
Similar comment to the above, both the ABI and gcc provide a single overload for each signed/unsigned version of this (no vector bool long long parameter overloads). 

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Comment at: lib/Headers/altivec.h:3640
@@ +3639,3 @@
+static vector long long __ATTRS_o_ai
+vec_vminsd(vector bool long long __a, vector long long __b)
+{
----------------
Same comment about overloads, ABI/gcc have only one.

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Comment at: lib/Headers/altivec.h:4042
@@ +4041,3 @@
+static vector unsigned long long __attribute__((__always_inline__))
+vec_vmuleuw(vector unsigned int __a, vector unsigned int __b)
+{
----------------
Since the forms that are not type-generic are deprecated in the ABI, do we really want to add new ones? I suppose that for consistency, this is valuable.

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Comment at: lib/Headers/altivec.h:4178
@@ +4177,3 @@
+static vector unsigned long long __attribute__((__always_inline__))
+vec_vmulouw(vector unsigned int __a, vector unsigned int __b)
+{
----------------
Similar comment about deprecated forms that are not type-generic.

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Comment at: lib/Headers/altivec.h:6938
@@ +6937,3 @@
+{
+  return __a >> (vector long long)__b;
+}
----------------
I am probably missing something, but it seems unclear to me how this will generate the expected instruction. If this code generates an "shr" in the IR and the back end generates a "vsrd" instruction when it sees the corresponding builtin, what tells the back end to emit the instruction when it sees a shift in the IR?

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Comment at: lib/Headers/altivec.h:11318
@@ +11317,3 @@
+#ifdef __POWER8_VECTOR__
+static long long __ATTRS_o_ai
+vec_all_eq(vector long long __a, vector long long __b)
----------------
Why the change in the return type for these? All the other ones return int, this one involves a promotion from in to long long. And the return type in the ABI is int.

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Comment at: lib/Headers/altivec.h:11325
@@ +11324,3 @@
+static long long __ATTRS_o_ai
+vec_all_eq(vector long long __a, vector bool long long __b)
+{
----------------
Once again, more overloads than the ABI lists. I assume we want these as well.

http://reviews.llvm.org/D8041

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