r218256 - clang/test/CodeGen/mips-varargs.c: Fixup for -Asserts.

[Daniel Sanders]

> clang doesn't name instructions (as possible) with -Asserts. Then, you
> wouldn't expect names (%n or %xxx) would be identical.

Thanks. I've found the code that does this and it hints at it being for optimization of clang itself. Presumably, there's a significant memory saving or something along those lines.

> AFAIK, my buildbot, http://bb.pgr.jp/console , can catch failures with
> -Aseerts. He doesn't send emails with a few reasons.

Ok. Thanks

> -----Original Message-----
> From: NAKAMURA Takumi [mailto:geek4civic at gmail.com]
> Sent: 23 September 2014 15:56
> To: Daniel Sanders
> Cc: cfe-commits at cs.uiuc.edu
> Subject: Re: r218256 - clang/test/CodeGen/mips-varargs.c: Fixup for -
> Asserts.
> 
> clang doesn't name instructions (as possible) with -Asserts. Then, you
> wouldn't expect names (%n or %xxx) would be identical.
> 
> AFAIK, my buildbot, http://bb.pgr.jp/console , can catch failures with
> -Aseerts. He doesn't send emails with a few reasons.
> 
> 2014-09-23 18:17 GMT+09:00 Daniel Sanders <Daniel.Sanders at imgtec.com>:
> > Thanks for fixing this. I'm not sure why -Asserts changes the names though,
> could you explain?
> >
> > Also, am I right in assuming your buildbot caught this? I don't seem to have
> an email from it.
> >
> >> -----Original Message-----
> >> From: cfe-commits-bounces at cs.uiuc.edu [mailto:cfe-commits-
> >> bounces at cs.uiuc.edu] On Behalf Of NAKAMURA Takumi
> >> Sent: 22 September 2014 17:40
> >> To: cfe-commits at cs.uiuc.edu
> >> Subject: r218256 - clang/test/CodeGen/mips-varargs.c: Fixup for -Asserts.
> >>
> >> Author: chapuni
> >> Date: Mon Sep 22 11:40:05 2014
> >> New Revision: 218256
> >>
> >> URL: http://llvm.org/viewvc/llvm-project?rev=218256&view=rev
> >> Log:
> >> clang/test/CodeGen/mips-varargs.c: Fixup for -Asserts.
> >>
> >> Modified:
> >>     cfe/trunk/test/CodeGen/mips-varargs.c
> >>
> >> Modified: cfe/trunk/test/CodeGen/mips-varargs.c
> >> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-
> >> varargs.c?rev=218256&r1=218255&r2=218256&view=diff
> >>
> ==========================================================
> >> ====================
> >> --- cfe/trunk/test/CodeGen/mips-varargs.c (original)
> >> +++ cfe/trunk/test/CodeGen/mips-varargs.c Mon Sep 22 11:40:05 2014
> >> @@ -17,37 +17,36 @@ int test_v4i32(char *fmt, ...) {
> >>  }
> >>
> >>  // ALL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...)
> >> -// ALL: entry:
> >>  //
> >>  // O32:   %va = alloca i8*, align [[PTRALIGN:4]]
> >>  // N32:   %va = alloca i8*, align [[PTRALIGN:4]]
> >>  // N64:   %va = alloca i8*, align [[PTRALIGN:8]]
> >>  //
> >> -// ALL:   %va1 = bitcast i8** %va to i8*
> >> -// ALL:   call void @llvm.va_start(i8* %va1)
> >> -// ALL:   %ap.cur = load i8** %va, align [[PTRALIGN]]
> >> -//
> >> -// O32:   %0 = ptrtoint i8* %ap.cur to [[PTRTYPE:i32]]
> >> -// N32:   %0 = ptrtoint i8* %ap.cur to [[PTRTYPE:i32]]
> >> -// N64:   %0 = ptrtoint i8* %ap.cur to [[PTRTYPE:i64]]
> >> +// ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
> >> +// ALL:   call void @llvm.va_start(i8* [[VA1]])
> >> +// ALL:   [[AP_CUR:%.+]] = load i8** %va, align [[PTRALIGN]]
> >> +//
> >> +// O32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[PTRTYPE:i32]]
> >> +// N32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[PTRTYPE:i32]]
> >> +// N64:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[PTRTYPE:i64]]
> >>  //
> >>  // Vectors are 16-byte aligned, however the O32 ABI has a maximum
> >> alignment of
> >>  // 8-bytes since the base of the stack is 8-byte aligned.
> >> -// O32:   %1 = add i32 %0, 7
> >> -// O32:   %2 = and i32 %1, -8
> >> +// O32:   [[PTR1:%.+]] = add i32 [[PTR0]], 7
> >> +// O32:   [[PTR2:%.+]] = and i32 [[PTR1]], -8
> >>  //
> >> -// N32:   %1 = add i32 %0, 15
> >> -// N32:   %2 = and i32 %1, -16
> >> +// N32:   [[PTR1:%.+]] = add i32 [[PTR0]], 15
> >> +// N32:   [[PTR2:%.+]] = and i32 [[PTR1]], -16
> >>  //
> >> -// N64:   %1 = add i64 %0, 15
> >> -// N64:   %2 = and i64 %1, -16
> >> +// N64:   [[PTR1:%.+]] = add i64 [[PTR0]], 15
> >> +// N64:   [[PTR2:%.+]] = and i64 [[PTR1]], -16
> >>  //
> >> -// ALL:   %3 = inttoptr [[PTRTYPE]] %2 to <4 x i32>*
> >> -// ALL:   %4 = inttoptr [[PTRTYPE]] %2 to i8*
> >> -// ALL:   %ap.next = getelementptr i8* %4, [[PTRTYPE]] 16
> >> -// ALL:   store i8* %ap.next, i8** %va, align [[PTRALIGN]]
> >> -// ALL:   %5 = load <4 x i32>* %3, align 16
> >> -// ALL:   call void @llvm.va_end(i8* %va1)
> >> -// ALL:   %vecext = extractelement <4 x i32> %5, i32 0
> >> -// ALL:   ret i32 %vecext
> >> +// ALL:   [[PTR3:%.+]] = inttoptr [[PTRTYPE]] [[PTR2]] to <4 x i32>*
> >> +// ALL:   [[PTR4:%.+]] = inttoptr [[PTRTYPE]] [[PTR2]] to i8*
> >> +// ALL:   [[AP_NEXT:%.+]] = getelementptr i8* [[PTR4]], [[PTRTYPE]] 16
> >> +// ALL:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
> >> +// ALL:   [[PTR5:%.+]] = load <4 x i32>* [[PTR3]], align 16
> >> +// ALL:   call void @llvm.va_end(i8* [[VA1]])
> >> +// ALL:   [[VECEXT:%.+]] = extractelement <4 x i32> [[PTR5]], i32 0
> >> +// ALL:   ret i32 [[VECEXT]]
> >>  // ALL: }
> >>
> >>
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