[PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post - LLVM

Tim Northover t.p.northover at gmail.com
Mon Nov 25 02:45:28 PST 2013

> This sounds good, and we are suggesting using EXTRACT_SUBREG and friends, so
> we are on the same page, right?

I'm not suggesting creating the EXTRACT_SUBREGs as a special-case in
AArch64 code, but leaving it to generic handling of shuffles. The less
special-cases we have to deal with, the better.

> I don't understand about this. Can you explicitly point out what intrinsics
> names are really unnecessary?

These two are distinct intrinsics:

{ <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8*, <16 x i8>,
<16 x i8>, i32, i32)
{ <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8
x i8>, i32, i32)

The first maps directly to the AArch64 instruction, the second needs
backend hacks to put it into a form suitable for precisely the same
instruction as the first.



More information about the cfe-commits mailing list