r194407 - [AArch64] The shift right/left and insert immediate builtins expect 3

[Chad Rosier]

Author: mcrosier
Date: Mon Nov 11 13:11:19 2013
New Revision: 194407

URL: http://llvm.org/viewvc/llvm-project?rev=194407&view=rev
Log:
[AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

Modified:
    cfe/trunk/include/clang/Basic/arm_neon.td
    cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c

Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=194407&r1=194406&r2=194407&view=diff
==============================================================================
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Mon Nov 11 13:11:19 2013
@@ -859,9 +859,9 @@ def SCALAR_SQSHL_N: SInst<"vqshl_n", "ss
 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
 
 // Shift Right And Insert (Immediate)
-def SCALAR_SRI_N: SInst<"vsri_n", "ssi", "SlSUl">;
+def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
 // Shift Left And Insert (Immediate)
-def SCALAR_SLI_N: SInst<"vsli_n", "ssi", "SlSUl">;
+def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
 
 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;

Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=194407&r1=194406&r2=194407&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Mon Nov 11 13:11:19 2013
@@ -7616,28 +7616,28 @@ int64_t test_vqshlud_n_s64(int64_t a) {
   return (int64_t)vqshlud_n_s64(a, 63);
 }
 
-int64_t test_vsrid_n_s64(int64_t a) {
+int64_t test_vsrid_n_s64(int64_t a, int64_t b) {
 // CHECK-LABEL: test_vsrid_n_s64
 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (int64_t)vsrid_n_s64(a, 63);
+  return (int64_t)vsrid_n_s64(a, b, 63);
 }
 
-uint64_t test_vsrid_n_u64(uint64_t a) {
+uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) {
 // CHECK-LABEL: test_vsrid_n_u64
 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (uint64_t)vsrid_n_u64(a, 63);
+  return (uint64_t)vsrid_n_u64(a, b, 63);
 }
 
-int64_t test_vslid_n_s64(int64_t a) {
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
 // CHECK-LABEL: test_vslid_n_s64
 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (int64_t)vslid_n_s64(a, 63);
+  return (int64_t)vslid_n_s64(a, b, 63);
 }
 
-uint64_t test_vslid_n_u64(uint64_t a) {
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
 // CHECK-LABEL: test_vslid_n_u64
 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (uint64_t)vslid_n_u64(a, 63);
+  return (uint64_t)vslid_n_u64(a, b, 63);
 }
 
 int8_t test_vqshrnh_n_s16(int16_t a) {