[PATCH][AArch64] implement aarch64 neon load/store instructions class AdvSIMD (lselem)

[Hao Liu]

Hi Tim,

I've added the refactored patch. Also add them online:
http://llvm-reviews.chandlerc.com/D1869.

This version 3 patch uses 6 super registers:
DPair/QPair/DTriple/QTriple/DQuad/QQuad to represent 2/3/4 consecutive
registers. Now there is no such problem with MVT::Untyped.

As there are currently no ACLE functions for ld1/st1 with consecutive
registers (only for ld1_1d/st1_1d), I'll add the missing ACLE functions when
they are created in the future (It's not difficult as they are similar to
ldn/stn). E.g. there is no ACLE function for ld1 {v0.2d, v1.2d}, [x0]. (we
only have an ACLE function for ld2 {v0.2d, v1.2d}, [x0]). 

Thanks,
-Hao

-----Original Message-----
From: Tim Northover [mailto:t.p.northover at gmail.com] 
Sent: Wednesday, October 09, 2013 8:58 AM
To: Hao Liu
Cc: llvm-commits; cfe-commits at cs.uiuc.edu
Subject: Re: [PATCH][AArch64] implement aarch64 neon load/store instructions
class AdvSIMD (lselem)

Hi Hao,

> OK, look forward to your patch.

I've committed the enabling as r192282. Hopefully that particular problem
should disappear for you now.

Cheers.

Tim.
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