[PATCH][AArch64] implement aarch64 neon load/store instructions class AdvSIMD (lselem)

[Tim Northover]

Hi Hao,

> The problem of DTriple/QTriple is that we don't have v3i64/v6i64, we can't
> use that 2 functions in AArch64ISelLowering.cpp. So we use MVT::Untype
> instead. We have to do something to MVT::Untype, or the test will fail.

Yep. I'd probably make all the other ones untyped to (DPair, QPair,
...). They're not really valid vector types in the normal LLVM sense.

> In SelectVST(), I use MVT::Untype to generate DTriple/QTriple directly as
> your comment.  But ld.ll will fail when it is compiling st3.
> $ ./Debug+Asserts/bin/llc -march=aarch64 -mattr=+neon < st.ll
> ...
> Running pass 'AArch64 Instruction Selection' on function '@test_vst3q_s8'
> Segmentation fault (core dumped)

Interesting. It's the DAG scheduler that's causing problems, rather
than actual instruction selection (it's trying to find out about
register-pressure based on type). If you pass "-enable-misched" to llc
then it gets a lot further in.

It still fails, but after types are dropped, so for a completely
different reason.

> BTW, if we make v4i64/v8i64 addRegisterClass legal by using addRegClass(),
> there will also be some problem in CopyPhysReg.

Yes, it'll also expect to be able to add v4i64s and so on. That's not
a good option, I think.

> Do you know how to solve this, or I did something wrong?

I'm very tempted to say we should just switch AArch64 over to the
MISched, since the other one is going away soon anyway.

I'll try to run some tests this evening to make sure everything works
and then send a patch to the list suggesting it. I think Ana was in
favour of the idea anyway when it came up last year.

What do you (or anyone else) think?

Cheers.

Tim.