r192045 - Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when
Nick Lewycky
nicholas at mxc.ca
Sat Oct 5 13:14:28 PDT 2013
Author: nicholas
Date: Sat Oct 5 15:14:27 2013
New Revision: 192045
URL: http://llvm.org/viewvc/llvm-project?rev=192045&view=rev
Log:
Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when
it is enabled. Also enable it on the same architectures that GCC does.
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/Preprocessor/x86_target_features.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=192045&r1=192044&r2=192045&view=diff
==============================================================================
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Sat Oct 5 15:14:27 2013
@@ -1064,6 +1064,7 @@ def mrtm : Flag<["-"], "mrtm">, Group<m_
def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
+def mcx16 : Flag<["-"], "mcx16">, Group<m_x86_Features_Group>;
def mips16 : Flag<["-"], "mips16">, Group<m_Group>;
def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_Group>;
def mmicromips : Flag<["-"], "mmicromips">, Group<m_Group>;
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=192045&r1=192044&r2=192045&view=diff
==============================================================================
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Sat Oct 5 15:14:27 2013
@@ -1596,6 +1596,7 @@ class X86TargetInfo : public TargetInfo
bool HasF16C;
bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
bool HasSHA;
+ bool HasCX16;
/// \brief Enumeration of all of the X86 CPUs supported by Clang.
///
@@ -1756,7 +1757,8 @@ public:
HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
- HasAVX512PF(false), HasSHA(false), CPU(CK_Generic), FPMath(FP_Default) {
+ HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
+ FPMath(FP_Default) {
BigEndian = false;
LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
}
@@ -2006,27 +2008,34 @@ void X86TargetInfo::getDefaultFeatures(l
case CK_Prescott:
case CK_Nocona:
setFeatureEnabledImpl(Features, "sse3", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Core2:
setFeatureEnabledImpl(Features, "ssse3", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Penryn:
setFeatureEnabledImpl(Features, "sse4.1", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Atom:
setFeatureEnabledImpl(Features, "ssse3", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Silvermont:
setFeatureEnabledImpl(Features, "sse4.2", true);
setFeatureEnabledImpl(Features, "aes", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "pclmul", true);
break;
case CK_Corei7:
setFeatureEnabledImpl(Features, "sse4.2", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_Corei7AVX:
setFeatureEnabledImpl(Features, "avx", true);
setFeatureEnabledImpl(Features, "aes", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "pclmul", true);
break;
case CK_CoreAVXi:
@@ -2047,6 +2056,7 @@ void X86TargetInfo::getDefaultFeatures(l
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
setFeatureEnabledImpl(Features, "fma", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_KNL:
setFeatureEnabledImpl(Features, "avx512f", true);
@@ -2107,6 +2117,7 @@ void X86TargetInfo::getDefaultFeatures(l
case CK_BTVER1:
setFeatureEnabledImpl(Features, "ssse3", true);
setFeatureEnabledImpl(Features, "sse4a", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "popcnt", true);
break;
@@ -2118,12 +2129,14 @@ void X86TargetInfo::getDefaultFeatures(l
setFeatureEnabledImpl(Features, "pclmul", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "f16c", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_BDVER1:
setFeatureEnabledImpl(Features, "xop", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "aes", true);
setFeatureEnabledImpl(Features, "pclmul", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_BDVER2:
setFeatureEnabledImpl(Features, "xop", true);
@@ -2134,6 +2147,7 @@ void X86TargetInfo::getDefaultFeatures(l
setFeatureEnabledImpl(Features, "fma", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "tbm", true);
+ setFeatureEnabledImpl(Features, "cx16", true);
break;
case CK_C3_2:
setFeatureEnabledImpl(Features, "sse", true);
@@ -2409,6 +2423,11 @@ bool X86TargetInfo::HandleTargetFeatures
continue;
}
+ if (Feature == "cx16") {
+ HasCX16 = true;
+ continue;
+ }
+
assert(Features[i][0] == '+' && "Invalid target feature!");
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
.Case("avx512f", AVX512F)
@@ -2684,6 +2703,9 @@ void X86TargetInfo::getTargetDefines(con
if (HasSHA)
Builder.defineMacro("__SHA__");
+ if (HasCX16)
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
+
// Each case falls through to the previous one here.
switch (SSELevel) {
case AVX512F:
@@ -2762,6 +2784,8 @@ bool X86TargetInfo::hasFeature(StringRef
.Case("avx512pf", HasAVX512PF)
.Case("bmi", HasBMI)
.Case("bmi2", HasBMI2)
+ .Case("cx16", HasCX16)
+ .Case("f16c", HasF16C)
.Case("fma", HasFMA)
.Case("fma4", XOPLevel >= FMA4)
.Case("tbm", HasTBM)
@@ -2787,7 +2811,6 @@ bool X86TargetInfo::hasFeature(StringRef
.Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
.Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
.Case("xop", XOPLevel >= XOP)
- .Case("f16c", HasF16C)
.Default(false);
}
Modified: cfe/trunk/test/Preprocessor/x86_target_features.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/x86_target_features.c?rev=192045&r1=192044&r2=192045&view=diff
==============================================================================
--- cfe/trunk/test/Preprocessor/x86_target_features.c (original)
+++ cfe/trunk/test/Preprocessor/x86_target_features.c Sat Oct 5 15:14:27 2013
@@ -211,3 +211,7 @@
// RUN: %clang -target i386-unknown-unknown -march=bdver2 -mno-tbm -x c -E -dM -o - %s | FileCheck --check-prefix=NOTBM %s
// NOTBM-NOT: #define __TBM__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
+
+// MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
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