[PATCH] Add support for poly16 vtst and vtstq

[Amaury de la Vieuville]

vtst and vtstq currently support poly8 types, but they should also work on
poly16.

http://llvm-reviews.chandlerc.com/D1698

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/aarch64-neon-intrinsics.c
  test/CodeGen/arm_neon_intrinsics.c

Index: include/clang/Basic/arm_neon.td
===================================================================
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -232,7 +232,7 @@
 def VCAGT : IInst<"vcagt", "udd", "fQf">;
 def VCALT : IInst<"vcalt", "udd", "fQf">;
 }
-def VTST  : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">;
+def VTST  : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // E.3.5 Absolute Difference
@@ -539,7 +539,7 @@
 def FCALE : IInst<"vcale", "udd", "fQfQd">;
 def FCALT : IInst<"vcalt", "udd", "fQfQd">;
 // With additional Ql, QUl, Qd types.
-def CMTST  : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQlQUcQUsQUiQUlQPc">;
+def CMTST  : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
 def CFMEQ  : SOpInst<"vceq", "udd",
                   "csifUcUsUiPcQcQsQiQlQfQUcQUsQUiQUlQPcQd", OP_EQ>;
 def CFMGE  : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GE>;
Index: test/CodeGen/aarch64-neon-intrinsics.c
===================================================================
--- test/CodeGen/aarch64-neon-intrinsics.c
+++ test/CodeGen/aarch64-neon-intrinsics.c
@@ -1095,12 +1095,24 @@
   // CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
 }
 
+uint16x4_t test_vtst_p16(poly16x4_t v1, poly16x4_t v2) {
+   // CHECK: test_vtst_p16
+  return vtst_p16(v1, v2);
+  // CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+}
+
 uint8x16_t test_vtstq_p8(poly8x16_t v1, poly8x16_t v2) {
    // CHECK: test_vtstq_p8
   return vtstq_p8(v1, v2);
   // CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
 }
 
+uint16x8_t test_vtstq_p16(poly16x8_t v1, poly16x8_t v2) {
+   // CHECK: test_vtstq_p16
+  return vtstq_p16(v1, v2);
+  // CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+}
+
 
 uint8x8_t test_vceq_s8(int8x8_t v1, int8x8_t v2) {
   // CHECK: test_vceq_s8
Index: test/CodeGen/arm_neon_intrinsics.c
===================================================================
--- test/CodeGen/arm_neon_intrinsics.c
+++ test/CodeGen/arm_neon_intrinsics.c
@@ -11361,6 +11361,12 @@
   return vtst_p8(a, b);
 }
 
+// CHECK: test_vtst_p16
+// CHECK: vtst.16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+uint16x4_t test_vtst_p16(poly16x4_t a, poly16x4_t b) {
+  return vtst_p16(a, b);
+}
+
 // CHECK: test_vtstq_s8
 // CHECK: vtst.8 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
 uint8x16_t test_vtstq_s8(int8x16_t a, int8x16_t b) {
@@ -11403,6 +11409,12 @@
   return vtstq_p8(a, b);
 }
 
+// CHECK: test_vtstq_p16
+// CHECK: vtst.16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+uint16x8_t test_vtstq_p16(poly16x8_t a, poly16x8_t b) {
+  return vtstq_p16(a, b);
+}
+
 
 // CHECK: test_vuzp_s8
 // CHECK: vuzp.8 d{{[0-9]+}}, d{{[0-9]+}}
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