r184601 - [NVPTX] Fix inline asm test case to use LLVM IR instead of PTX so it works even when the NVPTX target is not built
Justin Holewinski
jholewinski at nvidia.com
Fri Jun 21 15:39:56 PDT 2013
Author: jholewinski
Date: Fri Jun 21 17:39:56 2013
New Revision: 184601
URL: http://llvm.org/viewvc/llvm-project?rev=184601&view=rev
Log:
[NVPTX] Fix inline asm test case to use LLVM IR instead of PTX so it works even when the NVPTX target is not built
Modified:
cfe/trunk/test/CodeGen/nvptx-inlineasm-ptx.c
Modified: cfe/trunk/test/CodeGen/nvptx-inlineasm-ptx.c
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/nvptx-inlineasm-ptx.c?rev=184601&r1=184600&r2=184601&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/nvptx-inlineasm-ptx.c (original)
+++ cfe/trunk/test/CodeGen/nvptx-inlineasm-ptx.c Fri Jun 21 17:39:56 2013
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s
+// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s
void constraints() {
char c;
@@ -13,28 +13,28 @@ void constraints() {
float f;
double d;
- // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
+ // CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c"
asm volatile ("mov.b8 %0, %1;" : "=c"(c) : "c"(c));
- // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
+ // CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c"
asm volatile ("mov.b8 %0, %1;" : "=c"(uc) : "c"(uc));
- // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
+ // CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h"
asm volatile ("mov.b16 %0, %1;" : "=h"(s) : "h"(s));
- // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
+ // CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h"
asm volatile ("mov.b16 %0, %1;" : "=h"(us) : "h"(us));
- // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
+ // CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r"
asm volatile ("mov.b32 %0, %1;" : "=r"(i) : "r"(i));
- // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
+ // CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r"
asm volatile ("mov.b32 %0, %1;" : "=r"(ui) : "r"(ui));
- // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
+ // CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l"
asm volatile ("mov.b64 %0, %1;" : "=l"(l) : "l"(l));
- // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
+ // CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l"
asm volatile ("mov.b64 %0, %1;" : "=l"(ul) : "l"(ul));
- // CHECK: mov.b32 %f{{[0-9]+}}, %f{{[0-9]+}}
+ // CHECK: float asm sideeffect "mov.b32 $0, $1;", "=f,f"
asm volatile ("mov.b32 %0, %1;" : "=f"(f) : "f"(f));
- // CHECK: mov.b64 %fl{{[0-9]+}}, %fl{{[0-9]+}}
+ // CHECK: double asm sideeffect "mov.b64 $0, $1;", "=d,d"
asm volatile ("mov.b64 %0, %1;" : "=d"(d) : "d"(d));
}
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